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Message-ID: <20241127115804.2046576-2-thippeswamy.havalige@amd.com>
Date: Wed, 27 Nov 2024 17:28:03 +0530
From: Thippeswamy Havalige <thippeswamy.havalige@....com>
To: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
<manivannan.sadhasivam@...aro.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <jingoohan1@...il.com>,
<michal.simek@....com>, <bharat.kumar.gogada@....com>, Thippeswamy Havalige
<thippeswamy.havalige@....com>
Subject: [PATCH 1/2] dt-bindings: PCI: amd-mdb: Add YAML schemas for AMD Versal2 MDB PCIe Root Port Bridge
Add YAML dtschemas of AMD Versal2 MDB (Multimedia DMA Bridge) PCIe Root
Port Bridge dt binding.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
---
.../devicetree/bindings/pci/amd,mdb-pcie.yaml | 132 ++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml b/Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml
new file mode 100644
index 000000000000..ad9e447e87f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amd,mdb-pcie.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/amd,mdb-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD versal2 MDB(Multimedia DMA Bridge) Host Controller device tree
+
+maintainers:
+ - Thippeswamy Havalige <thippeswamy.havalige@....com>
+
+properties:
+ compatible:
+ const: amd,versal2-mdb-host
+
+ reg:
+ items:
+ - description: MDB PCIe controller 0 SLCR
+ - description: configuration region
+ - description: data bus interface
+ - description: address translation unit register
+
+ reg-names:
+ items:
+ - const: mdb_pcie_slcr
+ - const: config
+ - const: dbi
+ - const: atu
+
+ ranges:
+ maxItems: 2
+
+ msi-map:
+ maxItems: 1
+
+ bus-range:
+ maxItems: 1
+
+ "#address-cells":
+ const: 3
+
+ "#size-cells":
+ const: 2
+
+ device_type:
+ const: pci
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-map-mask:
+ items:
+ - const: 0
+ - const: 0
+ - const: 0
+ - const: 7
+
+ interrupt-map:
+ maxItems: 4
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-controller:
+ description: Interrupt controller node for handling legacy PCI interrupts.
+ type: object
+ properties:
+ interrupt-controller: true
+
+ "#address-cells":
+ const: 0
+
+ "#interrupt-cells":
+ const: 1
+
+ required:
+ - interrupt-controller
+ - "#address-cells"
+ - "#interrupt-cells"
+
+ additionalProperties: false
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-map
+ - interrupt-map-mask
+ - msi-map
+ - ranges
+ - "#interrupt-cells"
+ - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pci@...31000 {
+ compatible = "amd,versal2-mdb-host";
+ reg = <0x0 0xed931000 0x0 0x2000>,
+ <0x1000 0x100000 0x0 0xff00000>,
+ <0x1000 0x0 0x0 0x100000>,
+ <0x0 0xed860000 0x0 0x2000>;
+ reg-names = "mdb_pcie_slcr", "config", "dbi", "atu";
+ ranges = <0x2000000 0x00 0xa8000000 0x00 0xa8000000 0x00 0x10000000>,
+ <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>;
+ interrupts = <0 198 4>;
+ interrupt-parent = <&gic>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
+ <0 0 0 2 &pcie_intc_0 1>,
+ <0 0 0 3 &pcie_intc_0 2>,
+ <0 0 0 4 &pcie_intc_0 3>;
+ msi-map = <0x0 &gic_its 0x00 0x10000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ pcie_intc_0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
--
2.34.1
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