linux-kernel - Re: [PATCH v3 1/8] clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs

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Message-ID: <CAMuHMdUQd6AJe4b7hM_vqfW=NbVmv=zF9yr4bNBjJx05OXnEAA@mail.gmail.com>
Date: Wed, 27 Nov 2024 15:48:32 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: magnus.damm@...il.com, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org, 
	gregkh@...uxfoundation.org, jirislaby@...nel.org, p.zabel@...gutronix.de, 
	lethal@...ux-sh.org, g.liakhovetski@....de, linux-renesas-soc@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-serial@...r.kernel.org, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v3 1/8] clk: renesas: r9a08g045: Add clock, reset and
 power domain for the remaining SCIFs

On Fri, Nov 15, 2024 at 2:56 PM Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug
> console and is already enabled. Add the clock, reset and power domain
> support for the remaining ones.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-clk for v6.14.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds