[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <2lelgxo32rx6r2ivg2ni53re7c3kwvhyhtg6puwvvet7v5wpah@ysdqjscrgw7t>
Date: Thu, 28 Nov 2024 15:26:23 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Neil Armstrong <neil.armstrong@...aro.org>
Cc: Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Akhil P Oommen <quic_akhilpo@...cinc.com>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v3 7/7] arm64: qcom: dts: sm8650: add interconnect and
opp-peak-kBps for GPU
On Thu, Nov 28, 2024 at 11:25:47AM +0100, Neil Armstrong wrote:
> Each GPU OPP requires a specific peak DDR bandwidth, let's add
> those to each OPP and also the related interconnect path.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 25e47505adcb790d09f1d2726386438487255824..dc85ba8fe1d8f20981b6d7e9672fd7137b915b98 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2636,6 +2636,9 @@ gpu: gpu@...0000 {
> qcom,gmu = <&gmu>;
> #cooling-cells = <2>;
>
> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
QCOM_ICC_TAG_ALWAYS, LGTM otherwise
> + interconnect-names = "gfx-mem";
> +
> status = "disabled";
>
> zap-shader {
> @@ -2649,56 +2652,67 @@ gpu_opp_table: opp-table {
> opp-231000000 {
> opp-hz = /bits/ 64 <231000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
> + opp-peak-kBps = <2136718>;
> };
>
> opp-310000000 {
> opp-hz = /bits/ 64 <310000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
> + opp-peak-kBps = <6074218>;
> };
>
> opp-366000000 {
> opp-hz = /bits/ 64 <366000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
> + opp-peak-kBps = <6074218>;
> };
>
> opp-422000000 {
> opp-hz = /bits/ 64 <422000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <8171875>;
> };
>
> opp-500000000 {
> opp-hz = /bits/ 64 <500000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
> + opp-peak-kBps = <8171875>;
> };
>
> opp-578000000 {
> opp-hz = /bits/ 64 <578000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <12449218>;
> };
>
> opp-629000000 {
> opp-hz = /bits/ 64 <629000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
> + opp-peak-kBps = <12449218>;
> };
>
> opp-680000000 {
> opp-hz = /bits/ 64 <680000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <16500000>;
> };
>
> opp-720000000 {
> opp-hz = /bits/ 64 <720000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> + opp-peak-kBps = <16500000>;
> };
>
> opp-770000000 {
> opp-hz = /bits/ 64 <770000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + opp-peak-kBps = <16500000>;
> };
>
> opp-834000000 {
> opp-hz = /bits/ 64 <834000000>;
> opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + opp-peak-kBps = <16500000>;
> };
> };
> };
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
Powered by blists - more mailing lists