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Message-ID: <c2d74a3e-5aaa-4568-aa28-189b7d1b48b0@linaro.org>
Date: Thu, 28 Nov 2024 15:16:42 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Akhil P Oommen <quic_akhilpo@...cinc.com>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v3 6/7] arm64: qcom: dts: sm8550: add interconnect and
opp-peak-kBps for GPU
On 28/11/2024 14:26, Dmitry Baryshkov wrote:
> On Thu, Nov 28, 2024 at 11:25:46AM +0100, Neil Armstrong wrote:
>> Each GPU OPP requires a specific peak DDR bandwidth, let's add
>> those to each OPP and also the related interconnect path.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index e7774d32fb6d2288748ecec00bf525b2b3c40fbb..545eb52174c704bbefa69189fad9fbff053d8569 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -2114,6 +2114,9 @@ gpu: gpu@...0000 {
>> qcom,gmu = <&gmu>;
>> #cooling-cells = <2>;
>>
>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
>
> QCOM_ICC_TAG_ALWAYS
Damn, thanks forgot those one.
Thanks,
Neil
>
> LGTM otherwise.
>
>> + interconnect-names = "gfx-mem";
>> +
>> status = "disabled";
>>
>> zap-shader {
>> @@ -2127,41 +2130,49 @@ gpu_opp_table: opp-table {
>> opp-680000000 {
>> opp-hz = /bits/ 64 <680000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> + opp-peak-kBps = <16500000>;
>> };
>>
>> opp-615000000 {
>> opp-hz = /bits/ 64 <615000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
>> + opp-peak-kBps = <16500000>;
>> };
>>
>> opp-550000000 {
>> opp-hz = /bits/ 64 <550000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> + opp-peak-kBps = <12449218>;
>> };
>>
>> opp-475000000 {
>> opp-hz = /bits/ 64 <475000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
>> + opp-peak-kBps = <8171875>;
>> };
>>
>> opp-401000000 {
>> opp-hz = /bits/ 64 <401000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + opp-peak-kBps = <6671875>;
>> };
>>
>> opp-348000000 {
>> opp-hz = /bits/ 64 <348000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>> + opp-peak-kBps = <6074218>;
>> };
>>
>> opp-295000000 {
>> opp-hz = /bits/ 64 <295000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>> + opp-peak-kBps = <6074218>;
>> };
>>
>> opp-220000000 {
>> opp-hz = /bits/ 64 <220000000>;
>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>> + opp-peak-kBps = <6074218>;
>> };
>> };
>> };
>>
>> --
>> 2.34.1
>>
>
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