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Message-ID: <f14714b4bb667d339e6402c6cae37cee47406770.camel@linaro.org>
Date: Fri, 29 Nov 2024 11:24:32 +0000
From: André Draszik <andre.draszik@...aro.org>
To: Catalin Marinas <catalin.marinas@....com>, Will Deacon
 <will@...nel.org>,  Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Rob
 Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,  Conor
 Dooley <conor+dt@...nel.org>, Jagan Sridharan <badhri@...gle.com>, Alim
 Akhtar <alim.akhtar@...sung.com>
Cc: Peter Griffin <peter.griffin@...aro.org>, Tudor Ambarus
 <tudor.ambarus@...aro.org>, Sam Protsenko <semen.protsenko@...aro.org>,
 Will McVicker <willmcvicker@...gle.com>, Roy Luo <royluo@...gle.com>,
 kernel-team@...roid.com,  linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org,  linux-usb@...r.kernel.org,
 devicetree@...r.kernel.org,  linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH 4/6] arm64: dts: exynos: gs101: enable
 snps,dis_rxdet_inp3_quirk for DWC3

On Wed, 2024-11-27 at 11:01 +0000, André Draszik wrote:
> This is required for the DWC3 core to reliably detect the connected
> phy's Vbus state.
> 
> Signed-off-by: André Draszik <andre.draszik@...aro.org>
> ---
>  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 18d4e7852a1a..ab016fe9b99a 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1302,6 +1302,7 @@ usbdrd31_dwc3: usb@0 {
>  				interrupts = <GIC_SPI 463
> IRQ_TYPE_LEVEL_HIGH 0>;
>  				phys = <&usbdrd31_phy 0>, <&usbdrd31_phy
> 1>;
>  				phy-names = "usb2-phy", "usb3-phy";
> +				snps,dis_rxdet_inp3_quirk;

Seems this alone isn't enough in all cases, I'll send an update in a while.

Cheers,
Andre'


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