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Message-ID: <CAA8EJppDomrYvtJ46pi1_hDsf3zFeeTfrkQfVwE8UTN01KfKpw@mail.gmail.com>
Date: Fri, 29 Nov 2024 15:32:41 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Yongxing Mou <quic_yongmou@...cinc.com>
Cc: Ritesh Kumar <quic_riteshk@...cinc.com>, Rob Clark <robdclark@...il.com>,
Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 4/5] drm/msm/dpu: Add QCS8300 support
On Fri, 29 Nov 2024 at 12:01, Yongxing Mou <quic_yongmou@...cinc.com> wrote:
>
>
>
> On 2024/11/27 21:49, Dmitry Baryshkov wrote:
> > On Wed, Nov 27, 2024 at 03:05:04PM +0800, Yongxing Mou wrote:
> >> Add definitions for the display hardware used on the
> >> Qualcomm QCS8300 platform.
> >>
> >> Signed-off-by: Yongxing Mou <quic_yongmou@...cinc.com>
> >> ---
> >> .../drm/msm/disp/dpu1/catalog/dpu_8_4_qcs8300.h | 485 +++++++++++++++++++++
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> >> 4 files changed, 488 insertions(+)
> >>
> >>
> >
> > NAK, there is no need for this.
> Got it,thanks. will modify it in next patchset.Compared to sa8775p, they
> use same dpu but qcs8300 has one less intf and two fewer dp intfs. Other
> configurations are the same.can we reuse it or a new catalog file to
> show it.
Is it actually not populated in the silicon? What happens if one
access those INTF_n registers?
--
With best wishes
Dmitry
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