| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20241129153356.63547-3-antoniu.miclaus@analog.com>
Date: Fri, 29 Nov 2024 17:33:53 +0200
From: Antoniu Miclaus <antoniu.miclaus@...log.com>
To: <jic23@...nel.org>, <robh@...nel.org>, <conor+dt@...nel.org>,
<linux-iio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pwm@...r.kernel.org>
CC: Antoniu Miclaus <antoniu.miclaus@...log.com>
Subject: [PATCH v3 2/2] iio: frequency: adf4371: add ref doubler and div2
Add support for the reference doubler and the reference divide by 2
clock.
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@...log.com>
---
no changes in v3.
drivers/iio/frequency/adf4371.c | 34 +++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c
index b27088464826..b643a08f06ed 100644
--- a/drivers/iio/frequency/adf4371.c
+++ b/drivers/iio/frequency/adf4371.c
@@ -41,6 +41,12 @@
#define ADF4371_MOD2WORD_MSK GENMASK(5, 0)
#define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
+/* ADF4371_REG22 */
+#define ADF4371_REF_DOUB_MASK BIT(5)
+#define ADF4371_REF_DOUB(x) FIELD_PREP(ADF4371_REF_DOUB_MASK, x)
+#define ADF4371_RDIV2_MASK BIT(4)
+#define ADF4371_RDIV2(x) FIELD_PREP(ADF4371_RDIV2_MASK, x)
+
/* ADF4371_REG24 */
#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)
#define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)
@@ -70,6 +76,9 @@
#define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
#define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
+#define ADF4371_MIN_CLKIN_DOUB_FREQ 10000000ULL /* Hz */
+#define ADF4371_MAX_CLKIN_DOUB_FREQ 125000000ULL /* Hz */
+
/* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
#define ADF4371_MODULUS1 33554432ULL
/* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
@@ -175,6 +184,8 @@ struct adf4371_state {
unsigned int mod2;
unsigned int rf_div_sel;
unsigned int ref_div_factor;
+ bool ref_doubler_en;
+ bool ref_div2_en;
u8 buf[10] __aligned(IIO_DMA_MINALIGN);
};
@@ -476,6 +487,7 @@ static int adf4371_setup(struct adf4371_state *st)
{
unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
unsigned int vco_band_div, tmp;
+ struct device *dev = &st->spi->dev;
int ret;
/* Perform a software reset */
@@ -497,22 +509,40 @@ static int adf4371_setup(struct adf4371_state *st)
return ret;
}
+ st->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable");
+
+ st->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable");
+
/* Set address in ascending order, so the bulk_write() will work */
ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1));
if (ret < 0)
return ret;
+
+ if (st->ref_doubler_en &&
+ (st->clkin_freq > ADF4371_MAX_CLKIN_DOUB_FREQ ||
+ st->clkin_freq < ADF4371_MIN_CLKIN_DOUB_FREQ))
+ st->ref_doubler_en = false;
+
+ ret = regmap_update_bits(st->regmap, ADF4371_REG(0x22),
+ ADF4371_REF_DOUB_MASK |
+ ADF4371_RDIV2_MASK,
+ ADF4371_REF_DOUB(st->ref_doubler_en) |
+ ADF4371_RDIV2(st->ref_div2_en));
+ if (ret < 0)
+ return ret;
+
/*
* Calculate and maximize PFD frequency
* fPFD = REFIN × ((1 + D)/(R × (1 + T)))
* Where D is the REFIN doubler bit, T is the reference divide by 2,
* R is the reference division factor
- * TODO: it is assumed D and T equal 0.
*/
do {
st->ref_div_factor++;
- st->fpfd = st->clkin_freq / st->ref_div_factor;
+ st->fpfd = (st->clkin_freq * (st->ref_doubler_en ? 2 : 1)) /
+ (st->ref_div_factor * (st->ref_div2_en ? 2 : 1));
} while (st->fpfd > ADF4371_MAX_FREQ_PFD);
/* Calculate Timeouts */
--
2.47.1
Powered by blists - more mailing lists