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Message-ID: <3bdca75a-39aa-4ad8-a3f0-8124a0977c06@quicinc.com>
Date: Fri, 29 Nov 2024 11:13:28 +0800
From: Tingwei Zhang <quic_tingweiz@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Jingyi Wang
<quic_jingyw@...cinc.com>
CC: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Catalin Marinas
<catalin.marinas@....com>,
Will Deacon <will@...nel.org>, <quic_tengfan@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
Krzysztof Kozlowski <krzk@...nel.org>
Subject: Re: [PATCH v3 4/4] arm64: dts: qcom: add base QCS8300 RIDE board
On 11/28/2024 9:29 PM, Dmitry Baryshkov wrote:
>> +#include "qcs8300.dtsi"
>> +/ {
>> + model = "Qualcomm Technologies, Inc. QCS8300 Ride";
>> + compatible = "qcom,qcs8300-ride", "qcom,qcs8300";
>> + chassis-type = "embedded";
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + clocks {
>> + xo_board_clk: xo-board-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <38400000>;
>> + };
>> +
>> + sleep_clk: sleep-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <32000>;
>> + };
> Move both clocks to the qcs8300.dtsi. If you wish, you can keep
> frequencies in the board DT file.
>
Dmirty,
Move xo clock and sleep clock to board DT from SoC DT are due to review
comments in [1] and [2].
As you and Krzysztof discussed in [3], there're pros and cons for
different solutions. There are three possible ways.
Put these two clocks in board DT is aligned with hardware. These two
clocks are provided by PMIC instead of SoC.
Put these two clocks in SoC DT can reduce duplication since they are not
supposed to be changed on different board.
Put these two clocks in SoC DT and set frequency in board DT.
We need a unify way to deal with this kind of nodes and keep it
consistent across Qualcomm SoC.
Who shall make this decision?
[1]https://lore.kernel.org/all/10914199-1e86-4a2e-aec8-2a48cc49ef14@kernel.org/
[2]https://lore.kernel.org/all/be8b573c-db4e-4eec-a9a6-3cd83d04156d@kernel.org/
[3]https://lore.kernel.org/all/4kopdkvbkrpcpzwteezm427ml5putqvzsnfkpmg76spsple7l5@mg7v3ihwxnit/
>> + };
>> +};
>> +
--
Thanks,
Tingwei
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