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Message-ID: <20241129195537.GA2770926@bhelgaas>
Date: Fri, 29 Nov 2024 13:55:37 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: kw@...ux.com, gregkh@...uxfoundation.org, arnd@...db.de,
lpieralisi@...nel.org, shuah@...nel.org, kishon@...nel.org,
aman1.gupta@...sung.com, p.rajanbabu@...sung.com,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
bhelgaas@...gle.com, linux-arm-msm@...r.kernel.org, robh@...nel.org,
linux-kselftest@...r.kernel.org, stable+noautosel@...nel.org
Subject: Re: [PATCH v2 1/4] PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and
BAR1/BAR3 as RESERVED
On Fri, Nov 29, 2024 at 02:54:12PM +0530, Manivannan Sadhasivam wrote:
> On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default and software
> cannot change the type. So mark the those BARs as 64bit BARs and also mark
> the successive BAR1/BAR3 as RESERVED BARs so that the EPF drivers cannot
> use them.
"Default" implies an initial setting that can be changed, but you say
"by default" and also "software cannot change the type." Can they be
anything *other* than 64-bit BARs?
If they're hardwired to be 64-bit BARs, I would just say that.
> Cc: stable+noautosel@...nel.org # depends on patch introducing only_64bit flag
If stable maintainers need to act on this, do they need to search for
the patch introducing only_64bit flag? That seems onerous; is there a
SHA1 that would make it easier?
> Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index e588fcc54589..f925c4ad4294 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -823,6 +823,10 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
> .msi_capable = true,
> .msix_capable = false,
> .align = SZ_4K,
> + .bar[BAR_0] = { .only_64bit = true, },
> + .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_2] = { .only_64bit = true, },
> + .bar[BAR_3] = { .type = BAR_RESERVED, },
> };
>
> static const struct pci_epc_features *
> --
> 2.25.1
>
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