linux-kernel - [PATCH v7 03/12] x86/msr-index: define AMD heterogeneous CPU related MSR

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Message-ID: <20241130140703.557-4-mario.limonciello@amd.com>
Date: Sat, 30 Nov 2024 08:06:54 -0600
From: Mario Limonciello <mario.limonciello@....com>
To: Borislav Petkov <bp@...en8.de>
CC: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
	"Dave Hansen" <dave.hansen@...ux.intel.com>, "maintainer:X86 ARCHITECTURE
 (32-BIT AND 64-BIT)" <x86@...nel.org>, "H . Peter Anvin" <hpa@...or.com>,
	"Rafael J . Wysocki" <rafael@...nel.org>, "Gautham R . Shenoy"
	<gautham.shenoy@....com>, Mario Limonciello <mario.limonciello@....com>,
	Perry Yuan <perry.yuan@....com>, Brijesh Singh <brijesh.singh@....com>, Peter
 Zijlstra <peterz@...radead.org>, Li RongQing <lirongqing@...du.com>, "open
 list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <linux-kernel@...r.kernel.org>,
	"open list:ACPI" <linux-acpi@...r.kernel.org>, "open list:AMD PSTATE DRIVER"
	<linux-pm@...r.kernel.org>, Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Subject: [PATCH v7 03/12] x86/msr-index: define AMD heterogeneous CPU related MSR

From: Perry Yuan <perry.yuan@....com>

Introduces new MSR registers for AMD hardware feedback support.
These registers enable the system to provide workload classification
and configuration capabilities.

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>
Signed-off-by: Perry Yuan <perry.yuan@....com>
Signed-off-by: Mario Limonciello <mario.limonciello@....com>
---
 arch/x86/include/asm/msr-index.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3ae84c3b8e6db..0cd5ffe50f4a4 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -712,6 +712,11 @@
 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
 
+/* AMD Hardware Feedback Support MSRs */
+#define AMD_WORKLOAD_CLASS_CONFIG      0xc0000500
+#define AMD_WORKLOAD_CLASS_ID          0xc0000501
+#define AMD_WORKLOAD_HRST              0xc0000502
+
 /* AMD Last Branch Record MSRs */
 #define MSR_AMD64_LBR_SELECT			0xc000010e
 
-- 
2.43.0