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Message-ID: <20241201174639.742000-12-dario.binacchi@amarulasolutions.com>
Date: Sun, 1 Dec 2024 18:46:11 +0100
From: Dario Binacchi <dario.binacchi@...rulasolutions.com>
To: linux-kernel@...r.kernel.org
Cc: linux-amarula@...rulasolutions.com,
Dario Binacchi <dario.binacchi@...rulasolutions.com>,
Abel Vesa <abelvesa@...nel.org>,
Fabio Estevam <festevam@...il.com>,
Michael Turquette <mturquette@...libre.com>,
Peng Fan <peng.fan@....com>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Sascha Hauer <s.hauer@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org
Subject: [PATCH v4 11/18] clk: imx: add hw API imx8m_anatop_get_clk_hw
Get the hw of a clock registered by the anatop module. This function is
preparatory for future developments.
Signed-off-by: Dario Binacchi <dario.binacchi@...rulasolutions.com>
- Added in v4
---
(no changes since v1)
drivers/clk/imx/clk.c | 26 ++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 6 ++++++
2 files changed, 32 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index df83bd939492..8a8473a77b7c 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -128,6 +128,32 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name)
}
EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name);
+#if defined(CONFIG_CLK_IMX8MM) || defined(CONFIG_CLK_IMX8MN) || \
+ defined(CONFIG_CLK_IMX8MP) || defined(CONFIG_CLK_IMX8MQ)
+struct clk_hw *imx8m_anatop_get_clk_hw(int id)
+{
+#if defined(CONFIG_CLK_IMX8MQ)
+ const char *compatible = "fsl,imx8mq-anatop";
+#else
+ const char *compatible = "fsl,imx8mm-anatop";
+#endif
+ struct device_node *np;
+ struct of_phandle_args args;
+ struct clk_hw *hw;
+
+ np = of_find_compatible_node(NULL, NULL, compatible);
+ args.np = np;
+ args.args_count = 1;
+ args.args[0] = id;
+ of_node_put(np);
+
+ hw = __clk_get_hw(of_clk_get_from_provider(&args));
+ pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw));
+ return hw;
+}
+EXPORT_SYMBOL_GPL(imx8m_anatop_get_clk_hw);
+#endif
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index aa5202f284f3..6b6af26f4f1e 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -487,4 +487,10 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
u32 reg, const char **parent_names,
u8 num_parents, const u32 *mux_table, u32 mask);
+
+#if defined(CONFIG_CLK_IMX8MM) || defined(CONFIG_CLK_IMX8MN) || \
+ defined(CONFIG_CLK_IMX8MP) || defined(CONFIG_CLK_IMX8MQ)
+struct clk_hw *imx8m_anatop_get_clk_hw(int id);
+#endif
+
#endif
--
2.43.0
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