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Message-Id: <20241202153937.27640-1-tsbogend@alpha.franken.de>
Date: Mon, 2 Dec 2024 16:39:36 +0100
From: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To: linux-mips@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] MIPS: kernel: Rename read/write_c0_ecc to read/writec0_errctl
CP0 register 26 is used as ECC register for legacy cores, but newer
cores (MIPS32/MIPS64) use it as an ErrCtl register. Since the kernel only
uses CP0 26 as ErrCtl register rename the access functions to the more
fitting name.
Signed-off-by: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
---
arch/mips/include/asm/mipsregs.h | 4 ++--
arch/mips/kernel/mips-mt.c | 7 +++----
arch/mips/kernel/spram.c | 4 ----
arch/mips/kernel/traps.c | 32 ++++++++++++++++----------------
4 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3c6ddc0c2c7a..c025558754d5 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2039,8 +2039,8 @@ do { \
#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
-#define read_c0_ecc() __read_32bit_c0_register($26, 0)
-#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
+#define read_c0_errctl() __read_32bit_c0_register($26, 0)
+#define write_c0_errctl(val) __write_32bit_c0_register($26, 0, val)
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index 37676a44fefb..2ef610650a9e 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -122,9 +122,8 @@ void mips_mt_set_cpuoptions(void)
unsigned long ectlval;
unsigned long itcblkgrn;
- /* ErrCtl register is known as "ecc" to Linux */
- ectlval = read_c0_ecc();
- write_c0_ecc(ectlval | (0x1 << 26));
+ ectlval = read_c0_errctl();
+ write_c0_errctl(ectlval | (0x1 << 26));
ehb();
#define INDEX_0 (0x80000000)
#define INDEX_8 (0x80000008)
@@ -145,7 +144,7 @@ void mips_mt_set_cpuoptions(void)
ehb();
/* Write out to ITU with CACHE op */
cache_op(Index_Store_Tag_D, INDEX_0);
- write_c0_ecc(ectlval);
+ write_c0_errctl(ectlval);
ehb();
printk("Mapped %ld ITC cells starting at 0x%08x\n",
((itcblkgrn & 0x7fe00000) >> 20), itc_base);
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 71c7e5e27567..dd31e3fffd24 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -26,10 +26,6 @@
#define ERRCTL_SPRAM (1 << 28)
-/* errctl access */
-#define read_c0_errctl(x) read_c0_ecc(x)
-#define write_c0_errctl(x) write_c0_ecc(x)
-
/*
* Different semantics to the set_c0_* function built by __BUILD_SET_C0
*/
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index dc29bd9656b0..4515125a93f1 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1705,10 +1705,10 @@ static inline __init void parity_protection_init(void)
l2parity &= l1parity;
/* Probe L1 ECC support */
- cp0_ectl = read_c0_ecc();
- write_c0_ecc(cp0_ectl | ERRCTL_PE);
+ cp0_ectl = read_c0_errctl();
+ write_c0_errctl(cp0_ectl | ERRCTL_PE);
back_to_back_c0_hazard();
- cp0_ectl = read_c0_ecc();
+ cp0_ectl = read_c0_errctl();
/* Probe L2 ECC support */
gcr_ectl = read_gcr_err_control();
@@ -1727,9 +1727,9 @@ static inline __init void parity_protection_init(void)
cp0_ectl |= ERRCTL_PE;
else
cp0_ectl &= ~ERRCTL_PE;
- write_c0_ecc(cp0_ectl);
+ write_c0_errctl(cp0_ectl);
back_to_back_c0_hazard();
- WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
+ WARN_ON(!!(read_c0_errctl() & ERRCTL_PE) != l1parity);
/* Configure L2 ECC checking */
if (l2parity)
@@ -1761,18 +1761,18 @@ static inline __init void parity_protection_init(void)
unsigned long errctl;
unsigned int l1parity_present, l2parity_present;
- errctl = read_c0_ecc();
+ errctl = read_c0_errctl();
errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
/* probe L1 parity support */
- write_c0_ecc(errctl | ERRCTL_PE);
+ write_c0_errctl(errctl | ERRCTL_PE);
back_to_back_c0_hazard();
- l1parity_present = (read_c0_ecc() & ERRCTL_PE);
+ l1parity_present = (read_c0_errctl() & ERRCTL_PE);
/* probe L2 parity support */
- write_c0_ecc(errctl|ERRCTL_L2P);
+ write_c0_errctl(errctl|ERRCTL_L2P);
back_to_back_c0_hazard();
- l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
+ l2parity_present = (read_c0_errctl() & ERRCTL_L2P);
if (l1parity_present && l2parity_present) {
if (l1parity)
@@ -1791,9 +1791,9 @@ static inline __init void parity_protection_init(void)
printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
- write_c0_ecc(errctl);
+ write_c0_errctl(errctl);
back_to_back_c0_hazard();
- errctl = read_c0_ecc();
+ errctl = read_c0_errctl();
printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
if (l1parity_present)
@@ -1812,11 +1812,11 @@ static inline __init void parity_protection_init(void)
case CPU_5KC:
case CPU_5KE:
case CPU_LOONGSON32:
- write_c0_ecc(0x80000000);
+ write_c0_errctl(0x80000000);
back_to_back_c0_hazard();
/* Set the PE bit (bit 31) in the c0_errctl register. */
printk(KERN_INFO "Cache parity protection %sabled\n",
- (read_c0_ecc() & 0x80000000) ? "en" : "dis");
+ (read_c0_errctl() & 0x80000000) ? "en" : "dis");
break;
case CPU_20KC:
case CPU_25KF:
@@ -1887,8 +1887,8 @@ asmlinkage void do_ftlb(void)
if ((cpu_has_mips_r2_r6) &&
(((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
- pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
- read_c0_ecc());
+ pr_err("FTLB error exception, cp0_errctl=0x%08x:\n",
+ read_c0_errctl());
pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
reg_val = read_c0_cacheerr();
pr_err("c0_cacheerr == %08x\n", reg_val);
--
2.35.3
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