linux-kernel - Re: [PATCH v7 09/12] x86/process: Clear hardware feedback history for AMD processors

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Message-ID: <20241202114003.GC8562@noisy.programming.kicks-ass.net>
Date: Mon, 2 Dec 2024 12:40:03 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Mario Limonciello <mario.limonciello@....com>
Cc: Borislav Petkov <bp@...en8.de>, Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
	"H . Peter Anvin" <hpa@...or.com>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	"Gautham R . Shenoy" <gautham.shenoy@....com>,
	Perry Yuan <perry.yuan@....com>,
	Brijesh Singh <brijesh.singh@....com>,
	Li RongQing <lirongqing@...du.com>,
	"open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <linux-kernel@...r.kernel.org>,
	"open list:ACPI" <linux-acpi@...r.kernel.org>,
	"open list:AMD PSTATE DRIVER" <linux-pm@...r.kernel.org>,
	Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Subject: Re: [PATCH v7 09/12] x86/process: Clear hardware feedback history
 for AMD processors

On Sat, Nov 30, 2024 at 08:07:00AM -0600, Mario Limonciello wrote:
> From: Perry Yuan <perry.yuan@....com>
> 
> Incorporate a mechanism within the context switching code to reset
> the hardware history for AMD processors. Specifically, when a task
> is switched in, the class ID was read and reset the hardware workload
> classification history of CPU firmware and then it start to trigger
> workload classification for the next running thread.
> 
> Signed-off-by: Perry Yuan <perry.yuan@....com>
> Co-developed-by: Mario Limonciello <mario.limonciello@....com>
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  arch/x86/kernel/process_32.c | 4 ++++
>  arch/x86/kernel/process_64.c | 4 ++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
> index 0917c7f25720b..0bb6391b9089b 100644
> --- a/arch/x86/kernel/process_32.c
> +++ b/arch/x86/kernel/process_32.c
> @@ -213,6 +213,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
>  	/* Load the Intel cache allocation PQR MSR. */
>  	resctrl_sched_in(next_p);
>  
> +	/* Reset hw history on AMD CPUs */
> +	if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS))
> +		wrmsrl(AMD_WORKLOAD_HRST, 0x1);
> +
>  	return prev_p;
>  }

Are you really going to support all this jazz on 32bit builds?