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Message-ID: <3b98a7c5-b8bf-4e96-b969-da1800813251@lunn.ch>
Date: Mon, 2 Dec 2024 15:32:19 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Nikita Yushchenko <nikita.yoush@...entembedded.com>
Cc: "Russell King (Oracle)" <linux@...linux.org.uk>,
Maxime Chevallier <maxime.chevallier@...tlin.com>,
Heiner Kallweit <hkallweit1@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
Michael Dege <michael.dege@...esas.com>,
Christian Mardmoeller <christian.mardmoeller@...esas.com>,
Dennis Ostermann <dennis.ostermann@...esas.com>
Subject: Re: [PATCH] net: phy: phy_ethtool_ksettings_set: Allow any supported
speed
On Mon, Dec 02, 2024 at 04:09:43PM +0500, Nikita Yushchenko wrote:
> > > Right now, 'ethtool -s tsn0 master-slave forced-slave' causes a call to
> > > driver's ethtool set_link_ksettings method. Which does error out for me
> > > because at the call time, speed field is 2500.
> >
> > Are you saying that the PHY starts in fixed-speed 2.5G mode?
> >
> > What does ethtool tsn0 say after boot and the link has come up but
> > before any ethtool settings are changed?
>
> On a freshly booted board, with /etc/systemd/network temporary moved away.
>
> (there are two identical boards, connected to each other)
>
> root@...-033:~# ip l show dev tsn0
> 19: tsn0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop state DOWN mode DEFAULT group default qlen 1000
> link/ether 3a:e3:5c:56:ba:bd brd ff:ff:ff:ff:ff:ff
>
> root@...-033:~# ethtool tsn0
> Settings for tsn0:
> Supported ports: [ MII ]
> Supported link modes: 2500baseT/Full
If it is a T1 PHY, we want it reporting 25000BaseT1/Full here. Having
T1 then probably allows us to unlock forced master/slave without
autoneg, and setting speeds above 1G without autoneg.
Given this is an out of tree driver, i can understand why it does not,
it means patching a number of in tree files.
https://www.marvell.com/products/automotive/88q4364.html
says it can actually do 2.5G/5G/10GBASE-T1 as defined by the IEEE
802.3ch standard.
I would be reluctant to make changes to phylib without a kernel
quality PHY driver queued for merging. So you might want to spend some
time cleaning up the code. FYI: I've not looked at 802.3ch, but if
that defines registers, i would expect the driver patches to actually
be split into helpers for standard defined registers any 3ch driver
can use, and a PHY driver gluing those together and accessing marvell
specific registers.
Andrew
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