[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <891bdd31-6b5b-4b6c-9c63-eb0b3d1389e4@oss.qualcomm.com>
Date: Mon, 2 Dec 2024 15:49:08 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>,
Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
Rajendra Nayak <quic_rjendra@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>,
Abel Vesa <abel.vesa@...aro.org>
Cc: Johan Hovold <johan+linaro@...nel.org>,
Sibi Sankar <quic_sibis@...cinc.com>, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts
flags
On 15.08.2024 10:40 PM, Bjorn Andersson wrote:
>
> On Thu, 01 Aug 2024 13:21:07 +0300, Abel Vesa wrote:
>> Allowing these GDSCs to collapse makes the QMP combo PHYs lose their
>> configuration on machine suspend. Currently, the QMP combo PHY driver
>> doesn't reinitialise the HW on resume. Under such conditions, the USB
>> SuperSpeed support is broken. To avoid this, mark the pwrsts flags with
>> RET_ON. This is in line with USB 2 PHY GDSC config.
Your commit text suggests adding simple system pm ops which
essentially re-run phy_init would fix the issue as well.
The docs say the PHY can retain state even throughout a CX
collapse, so this seems like a band-aid over a small cut.
Konrad
Powered by blists - more mailing lists