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Message-ID: <CAPYmKFvoEwec7NfMyaf=oO9jQz2o9Bvebunh=cvbNO_ESOnk5A@mail.gmail.com>
Date: Tue, 3 Dec 2024 21:37:35 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: Björn Töpel <bjorn@...nel.org>
Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, 
	lihangjing@...edance.com, xieyongji@...edance.com, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [External] Re: [PATCH] riscv: mm: Fix alignment of phys_ram_base

On Tue, Dec 3, 2024 at 7:50 PM Björn Töpel <bjorn@...nel.org> wrote:
>
> Xu Lu <luxu.kernel@...edance.com> writes:
>
> > This commit fixes the alignment of phys_ram_base in RISC-V.
> >
> > In sparse vmemmap model, the virtual address of vmemmap is calculated as:
> > '(struct page *)VMEMMAP_START - (phys_ram_base >> PAGE_SHIFT)'.
> > And the struct page's va can be calculated with an offset:
> > 'vmemmap + (pfn)'.
> >
> > However, when initializing struct pages, kernel actually starts from the
> > first page from the same section that phys_ram_base belongs to. If the
> > first page's physical address is not 'phys_ram_base >> PAGE_SHIFT', then
> > we get an va below VMEMMAP_START when calculating va for it's struct page.
>
> Nice catch! I managed to reproduce this on a hacked qemu virt machine.
>
> > For example, if phys_ram_base starts from 0x82000000 with pfn 0x82000, the
> > first page in the same section is actually pfn 0x80000. During
> > init_unavailage_range, we will initialize struct page for pfn 0x80000
>
> "init_unavailable_range()" spelling for greppability.
>
> > with virtual address '(struct page *)VMEMMAP_START - 0x2000', which is
> > below VMEMMAP_START as well as PCI_IO_END.
> >
> > This commit fixes this bug by aligning phys_ram_base with SECTION_SIZE.
> >
> > Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
>
> Please add a fixes tag.

Roger that.

>
> > ---
> >  arch/riscv/mm/init.c | 5 ++++-
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> > index 0e8c20adcd98..9866de267b74 100644
> > --- a/arch/riscv/mm/init.c
> > +++ b/arch/riscv/mm/init.c
> > @@ -59,6 +59,8 @@ EXPORT_SYMBOL(pgtable_l4_enabled);
> >  EXPORT_SYMBOL(pgtable_l5_enabled);
> >  #endif
> >
> > +#define RISCV_MEMSTART_ALIGN (1UL << SECTION_SIZE_BITS)
> > +
> >  phys_addr_t phys_ram_base __ro_after_init;
> >  EXPORT_SYMBOL(phys_ram_base);
> >
> > @@ -241,7 +243,8 @@ static void __init setup_bootmem(void)
> >        * at worst, we map the linear mapping with PMD mappings.
> >        */
> >       if (!IS_ENABLED(CONFIG_XIP_KERNEL))
> > -             phys_ram_base = memblock_start_of_DRAM() & PMD_MASK;
> > +             phys_ram_base = round_down(memblock_start_of_DRAM(),
> > +                                        RISCV_MEMSTART_ALIGN);
>
> No need to wrap this line. Also, is the RISCV_MEMSTART_ALIGN define
> really needed?

Maybe it is not so friendly to FLATMEM model if we always align
phys_ram_base with SECTION_SIZE.
I will refine the code and send again later.

>
> The kernel test robot had some build issues as well!
>
>
> Björn

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