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Message-ID: <2d7f8afc-119a-4080-93be-bf3daf017e5e@denx.de>
Date: Tue, 3 Dec 2024 21:15:10 +0100
From: Marek Vasut <marex@...x.de>
To: Nikolaus Voss <nv@...n.de>,
Alexander Stein <alexander.stein@...tq-group.com>,
Liu Ying <victor.liu@....com>, Luca Ceresoli <luca.ceresoli@...tlin.com>,
Fabio Estevam <festevam@...x.de>, Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>,
David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
miquel.raynal@...tlin.com, nikolaus.voss@...g-streit.com
Cc: dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] drm: bridge: fsl-ldb: fixup mode on freq mismatch
On 12/3/24 8:09 PM, Nikolaus Voss wrote:
> LDB clock has to be a fixed multiple of the pixel clock.
> As LDB and pixel clock are derived from different clock sources
Can you please share the content of /sys/kernel/debug/clk/clk_summary ?
LDB and matching LCDIF should use the same PLL on MX8MP , else you might
really run into odd issues.
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