linux-kernel - Re: [PATCH] drm: bridge: fsl-ldb: fixup mode on freq mismatch

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Message-ID: <12a1b86e-8f25-4875-8503-1de98f125a62@denx.de>
Date: Tue, 3 Dec 2024 04:12:33 +0100
From: Marek Vasut <marex@...x.de>
To: Liu Ying <victor.liu@....nxp.com>, Nikolaus Voss <nv@...n.de>
Cc: Alexander Stein <alexander.stein@...tq-group.com>,
 Liu Ying <victor.liu@....com>, Luca Ceresoli <luca.ceresoli@...tlin.com>,
 Fabio Estevam <festevam@...x.de>, Andrzej Hajda <andrzej.hajda@...el.com>,
 Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
 Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
 Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>,
 David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
 dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
 nikolaus.voss@...g-streit.com, miquel.raynal@...tlin.com
Subject: Re: [PATCH] drm: bridge: fsl-ldb: fixup mode on freq mismatch

On 12/3/24 3:22 AM, Liu Ying wrote:

[...]

>>> I doubt that pixel clock tree cannot find appropriate division ratios
>>> for some pixel clock rates, especially for dual-link LVDS on i.MX8MP
>>> and i.MX93 platforms, because PLL clock rate should be 7x faster than
>>> pixel clock rate and 2x faster than "ldb" clock rate so that the 3.5
>>> folder between "ldb" clock and pixel clock can be met. That means the
>>> PLL clock rate needs to be explicitly set first for this case.
>>>
>>> Can you assign the PLL clock rate in DT to satisfy the "ldb" and pixel
>>> clock rates like the below commit does, if you use a LVDS panel?
>>>
>>> 4fbb73416b10 ("arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1
>>> frequency to 506.8 MHz")
>>
>> I probably could. The point of my patch is you don't have to know in
>> advance which LVDS panel is connected, and you don't have to calculate
>> the base PLL clock by hand and store it in the device tree.
>>
>> In my test system, I have three different LVDS panels with EDID EEPROM,
>> none of which worked with the stock driver, but all work with this
>> patch.
>> With slightly adapted pixel clocks though.
> 
> If each of the three LVDS panels has only one display mode, you may
> assign the PLL clock rates in DT overlays for the panels.
I temporarily agree.

I also currently use DTOs for various panels including their PLL 
setting, but in the end, I think/hope the work of Miquel and co. is 
going to make that PLL setting part unnecessary.