linux-kernel - Re: [PATCH v7 09/12] x86/process: Clear hardware feedback history for AMD processors

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Message-ID: <4062ace2-7881-4621-ba3c-4d09bc58a23a@amd.com>
Date: Tue, 3 Dec 2024 15:56:35 -0600
From: Mario Limonciello <mario.limonciello@....com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Borislav Petkov <bp@...en8.de>, Thomas Gleixner <tglx@...utronix.de>,
 Ingo Molnar <mingo@...hat.com>, Dave Hansen <dave.hansen@...ux.intel.com>,
 "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
 "H . Peter Anvin" <hpa@...or.com>, "Rafael J . Wysocki" <rafael@...nel.org>,
 "Gautham R . Shenoy" <gautham.shenoy@....com>,
 Perry Yuan <perry.yuan@....com>, Brijesh Singh <brijesh.singh@....com>,
 Li RongQing <lirongqing@...du.com>,
 "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
 <linux-kernel@...r.kernel.org>, "open list:ACPI"
 <linux-acpi@...r.kernel.org>,
 "open list:AMD PSTATE DRIVER" <linux-pm@...r.kernel.org>,
 Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
Subject: Re: [PATCH v7 09/12] x86/process: Clear hardware feedback history for
 AMD processors

On 12/2/2024 09:59, Peter Zijlstra wrote:
> On Sat, Nov 30, 2024 at 08:07:00AM -0600, Mario Limonciello wrote:
>> From: Perry Yuan <perry.yuan@....com>
>>
>> Incorporate a mechanism within the context switching code to reset
>> the hardware history for AMD processors. Specifically, when a task
>> is switched in, the class ID was read and reset the hardware workload
>> classification history of CPU firmware and then it start to trigger
>> workload classification for the next running thread.
>>
>> Signed-off-by: Perry Yuan <perry.yuan@....com>
>> Co-developed-by: Mario Limonciello <mario.limonciello@....com>
>> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
>> ---
> 
>> diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
>> index 226472332a70d..371e0e8f987fa 100644
>> --- a/arch/x86/kernel/process_64.c
>> +++ b/arch/x86/kernel/process_64.c
>> @@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
>>   	/* Load the Intel cache allocation PQR MSR. */
>>   	resctrl_sched_in(next_p);
>>   
>> +	/* Reset hw history on AMD CPUs */
>> +	if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS))
>> +		wrmsrl(AMD_WORKLOAD_HRST, 0x1);
>> +
>>   	return prev_p;
>>   }
> 
> BTW, how many cycles for this WRMSR ?

When I measured it the average delay was ~119ns with a wider range of 
delays (standard deviation was 25% greater).

> 
> And, as already stated, I'm failing to find the actual classification
> code, but assuming that's RDMSR(s?), how much for them?
> 

As mentioned on patch 1 comments the current patch series doesn't use 
any classification data produced by the hardware.