linux-kernel - Re: [PATCH 8/9] arm64: dts: renesas: r8a779h0: Add display support

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Message-ID: <20241203093703.GL10736@pendragon.ideasonboard.com>
Date: Tue, 3 Dec 2024 11:37:03 +0200
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
Cc: Kieran Bingham <kieran.bingham+renesas@...asonboard.com>,
	Andrzej Hajda <andrzej.hajda@...el.com>,
	Neil Armstrong <neil.armstrong@...aro.org>,
	Robert Foss <rfoss@...nel.org>, Jonas Karlman <jonas@...boo.se>,
	Jernej Skrabec <jernej.skrabec@...il.com>,
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
	Maxime Ripard <mripard@...nel.org>,
	Thomas Zimmermann <tzimmermann@...e.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, LUU HOAI <hoai.luu.ub@...esas.com>,
	Jagan Teki <jagan@...rulasolutions.com>,
	Sam Ravnborg <sam@...nborg.org>,
	Biju Das <biju.das.jz@...renesas.com>,
	dri-devel@...ts.freedesktop.org, linux-renesas-soc@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-clk@...r.kernel.org,
	Tomi Valkeinen <tomi.valkeinen+renesas@...asonboard.com>
Subject: Re: [PATCH 8/9] arm64: dts: renesas: r8a779h0: Add display support

Hi Tomi,

Thank you for the patch.

On Tue, Dec 03, 2024 at 10:01:42AM +0200, Tomi Valkeinen wrote:
> From: Tomi Valkeinen <tomi.valkeinen+renesas@...asonboard.com>
> 
> Add the device nodes for supporting DU and DSI.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@...asonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 77 +++++++++++++++++++++++++++++++
>  1 file changed, 77 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> index 12d8be3fd579..82df6ee98afb 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
> @@ -1828,6 +1828,54 @@ csi41isp1: endpoint {
>  			};
>  		};
>  
> +		fcpvd0: fcp@...10000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xfea10000 0 0x200>;
> +			clocks = <&cpg CPG_MOD 508>;
> +			power-domains = <&sysc R8A779H0_PD_C4>;
> +			resets = <&cpg 508>;
> +		};
> +
> +		vspd0: vsp@...20000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfea20000 0 0x8000>;
> +			interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;

The documentation lists this interrupt as being LevelSensitive and
Negative. I wouldn't expect the VSP to work at all with a wrong polarity
in DT, so the level may get inverted somewhere.

> +			clocks = <&cpg CPG_MOD 830>;
> +			power-domains = <&sysc R8A779H0_PD_C4>;
> +			resets = <&cpg 830>;
> +			renesas,fcp = <&fcpvd0>;
> +		};
> +
> +		du: display@...00000 {
> +			compatible = "renesas,du-r8a779h0";
> +			reg = <0 0xfeb00000 0 0x40000>;
> +			interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 411>;
> +			clock-names = "du.0";
> +			power-domains = <&sysc R8A779H0_PD_C4>;
> +			resets = <&cpg 411>;
> +			reset-names = "du.0";
> +			renesas,vsps = <&vspd0 0>;
> +
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					du_out_dsi0: endpoint {
> +						remote-endpoint = <&dsi0_in>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};

On V4M the DU has a single channel, so there should be a single port.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>

> +			};
> +		};
> +
>  		isp0: isp@...00000 {
>  			compatible = "renesas,r8a779h0-isp",
>  				     "renesas,rcar-gen4-isp";
> @@ -1996,6 +2044,35 @@ isp1vin15: endpoint {
>  			};
>  		};
>  
> +		dsi0: dsi-encoder@...80000 {
> +			compatible = "renesas,r8a779h0-dsi-csi2-tx";
> +			reg = <0 0xfed80000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD 415>,
> +				 <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>,
> +				 <&cpg CPG_CORE R8A779H0_CLK_DSIREF>;
> +			clock-names = "fck", "dsi", "pll";
> +			power-domains = <&sysc R8A779H0_PD_C4>;
> +			resets = <&cpg 415>;
> +
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					dsi0_in: endpoint {
> +						remote-endpoint = <&du_out_dsi0>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};
> +			};
> +		};
> +
>  		prr: chipid@...00044 {
>  			compatible = "renesas,prr";
>  			reg = <0 0xfff00044 0 4>;

-- 
Regards,

Laurent Pinchart