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Message-Id: <20241204150326.1470749-3-quic_vdadhani@quicinc.com>
Date: Wed, 4 Dec 2024 20:33:21 +0530
From: Viken Dadhaniya <quic_vdadhani@...cinc.com>
To: andi.shyti@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, gregkh@...uxfoundation.org, jirislaby@...nel.org,
broonie@...nel.or, andersson@...nel.org, konradybcio@...nel.org,
johan+linaro@...nel.org, dianders@...omium.org, agross@...nel.org,
linux-arm-msm@...r.kernel.org, linux-i2c@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-serial@...r.kernel.org, linux-spi@...r.kernel.org
Cc: =quic_msavaliy@...cinc.com, quic_anupkulk@...cinc.com,
Viken Dadhaniya <quic_vdadhani@...cinc.com>,
Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>
Subject: [PATCH v1 2/7] spi: dt-bindings: Document DT properties for QUP firmware loading
Document the 'qcom,load-firmware' and 'qcom,xfer-mode' properties to
support SE(Serial Engine) firmware loading from the protocol driver and
to select the data transfer mode, either GPI DMA (Generic Packet Interface)
or non-GPI mode (PIO/CPU DMA).
SPI controller can operate in one of two modes based on the
'qcom,xfer-mode' property, and the firmware is loaded accordingly.
Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>
Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>
Signed-off-by: Viken Dadhaniya <quic_vdadhani@...cinc.com>
---
.../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index 2e20ca313ec1..7038981f54ff 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -66,6 +66,15 @@ properties:
reg:
maxItems: 1
+ qcom,load-firmware:
+ type: boolean
+ description: Optional property to load SE (serial engine) Firmware from protocol driver.
+
+ qcom,xfer-mode:
+ description: Value 1,2 and 3 represents FIFO, CPU DMA and GSI DMA mode respectively.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3]
+
required:
- compatible
- clocks
@@ -97,6 +106,8 @@ examples:
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
+ qcom,load-firmware;
+ qcom,xfer-mode = <1>;
};
- |
--
2.34.1
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