linux-kernel - Re: [PATCH v2 04/11] drm/msm: adreno: add GMU_BW

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CAL7siYM7MMrYtARvicp0+AAdP=drufHVgCAgcTOmSJxvS5_mvg@mail.gmail.com>
Date: Wed, 4 Dec 2024 16:33:09 +0800
From: Luoxi Li <lee.lockhey@...il.com>
To: Neil Armstrong <neil.armstrong@...aro.org>
Cc: Akhil P Oommen <quic_akhilpo@...cinc.com>, Viresh Kumar <vireshk@...nel.org>, 
	Nishanth Menon <nm@...com>, Stephen Boyd <sboyd@...nel.org>, "Rafael J. Wysocki" <rafael@...nel.org>, 
	Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>, 
	Konrad Dybcio <konradybcio@...nel.org>, Abhinav Kumar <quic_abhinavk@...cinc.com>, 
	Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>, 
	Simona Vetter <simona@...ll.ch>, Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Connor Abbott <cwabbott0@...il.com>, linux-pm@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, 
	dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org, 
	devicetree@...r.kernel.org
Subject: Re: [PATCH v2 04/11] drm/msm: adreno: add GMU_BW_VOTE feature flag

sry，Please ignore this email forwarding， thks.

Dmitry Baryshkov <lee.lockhey@...il.com> 于2024年12月4日周三 16:28写道：
>
> On Wed, Nov 20, 2024 at 01:37:48PM +0100, Neil Armstrong wrote:
> > On 20/11/2024 12:19, Dmitry Baryshkov wrote:
> > > On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
> > > > The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
> > > > along the Frequency and Power Domain level, but by default we leave the
> > > > OPP core vote for the interconnect ddr path.
> > > >
> > > > While scaling via the interconnect path was sufficient, newer GPUs
> > > > like the A750 requires specific vote paremeters and bandwidth to
> > > > achieve full functionality.
> > > >
> > > > While the feature will require some data in a6xx_info, it's safer
> > > > to only enable tested platforms with this flag first.
> > > >
> > > > Add a new feature enabling DDR Bandwidth vote via GMU.
> > >
> > > Squash into the implementation patch.
> >
> > Which one ? the flag is use in the next 3 patches
>
> First one which uses it
>
> >
> > >
> > > >
> > > > Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> > > > ---
> > > >   drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> > > >   1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > index 4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> > > > @@ -58,6 +58,7 @@ enum adreno_family {
> > > >   #define ADRENO_FEAT_HAS_HW_APRIV                BIT(0)
> > > >   #define ADRENO_FEAT_HAS_CACHED_COHERENT         BIT(1)
> > > >   #define ADRENO_FEAT_PREEMPTION                  BIT(2)
> > > > +#define ADRENO_FEAT_GMU_BW_VOTE                  BIT(3)
> > > >   /* Helper for formating the chip_id in the way that userspace tools like
> > > >    * crashdec expect.
> > > >
> > > > --
> > > > 2.34.1
> > > >
> > >
> >
>
> --
> With best wishes
> Dmitry
>
>
> ----- End forwarded message -----