linux-kernel - Re: [PATCH v4 3/3] can: flexcan: add NXP S32G2/S32G3 SoC support

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Message-ID: <1147e8d9-b6e1-4290-9cfa-888d93f185e9@oss.nxp.com>
Date: Wed, 4 Dec 2024 13:38:51 +0200
From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
To: Marc Kleine-Budde <mkl@...gutronix.de>
Cc: Vincent Mailhol <mailhol.vincent@...adoo.fr>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, linux-can@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 NXP S32 Linux <s32@....com>, imx@...ts.linux.dev,
 Christophe Lizzi <clizzi@...hat.com>, Alberto Ruiz <aruizrui@...hat.com>,
 Enric Balletbo <eballetb@...hat.com>
Subject: Re: [PATCH v4 3/3] can: flexcan: add NXP S32G2/S32G3 SoC support

On 12/4/2024 10:05 AM, Marc Kleine-Budde wrote:
> On 04.12.2024 09:49:15, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
>>
>> Add device type data for S32G2/S32G3 SoC.
>>
>> FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
>> management is different.
>>
>> On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
>> errors, Mailboxes 0-7 and Mailboxes 8-127 respectively.
>> In order to handle this FlexCAN hardware particularity, first reuse the
>> 'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq handling
>> support. Secondly, use the newly introduced
>> 'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk which handles the case where two
>> separate mailbox ranges are controlled by independent hardware interrupt
>> lines.
>>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
>> ---
> 
> Looks good to me!
> 
> Unrelated to this patch, but I want to extend the "FLEXCAN hardware
> feature flags" table in "flexcan.h". Can you provide the needed
> information?
> 

Hello Marc,

I would say the following S32G related information could be added:

>> /* FLEXCAN hardware feature flags
>>   *
>>   * Below is some version info we got:
>>   *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB
>>   *                                Filter? connected?  Passive detection  ption in MB Supported?
>>   * MCF5441X FlexCAN2  ?               no       yes        no       no        no           no     16
>>   *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>>   *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64
>>   *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64
>>   *    MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no           no     64
>>   *    MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes           no     64
>>   *    MX8QM FlexCAN3  03.00.23.00    yes       yes        no       no       yes          yes     64
>>   *    MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes     64
>>   *    VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no     64
>>   *  LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no     64
>>   *  LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes     64
      *  S32G2/S32G3 FlexCAN3  03.00.39.00     no       yes        no 
   yes       yes          yes     128
>>   *
>>   * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
>>   */
> 
> regards,
> Marc
> 

Would you like me to send another version of this patchset with above 
information included ?

Best Regards,
Ciprian