linux-kernel - [PATCH net-next v8 01/15] net: stmmac: Fix CSR divider comment

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Message-Id: <20241205-upstream_s32cc_gmac-v8-1-ec1d180df815@oss.nxp.com>
Date: Thu, 05 Dec 2024 17:42:58 +0100
From: Jan Petrous via B4 Relay <devnull+jan.petrous.oss.nxp.com@...nel.org>
To: Maxime Coquelin <mcoquelin.stm32@...il.com>, 
 Alexandre Torgue <alexandre.torgue@...s.st.com>, 
 Jose Abreu <joabreu@...opsys.com>, "David S. Miller" <davem@...emloft.net>, 
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, 
 Paolo Abeni <pabeni@...hat.com>, Vinod Koul <vkoul@...nel.org>, 
 Richard Cochran <richardcochran@...il.com>, Andrew Lunn <andrew@...n.ch>, 
 Heiner Kallweit <hkallweit1@...il.com>, 
 Russell King <linux@...linux.org.uk>, Shawn Guo <shawnguo@...nel.org>, 
 Sascha Hauer <s.hauer@...gutronix.de>, 
 Pengutronix Kernel Team <kernel@...gutronix.de>, 
 Fabio Estevam <festevam@...il.com>, Emil Renner Berthing <kernel@...il.dk>, 
 Minda Chen <minda.chen@...rfivetech.com>, 
 Nicolas Ferre <nicolas.ferre@...rochip.com>, 
 Claudiu Beznea <claudiu.beznea@...on.dev>, 
 Iyappan Subramanian <iyappan@...amperecomputing.com>, 
 Keyur Chudgar <keyur@...amperecomputing.com>, 
 Quan Nguyen <quan@...amperecomputing.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Giuseppe Cavallaro <peppe.cavallaro@...com>, 
 Andrew Lunn <andrew+netdev@...n.ch>
Cc: linux-stm32@...md-mailman.stormreply.com, 
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 netdev@...r.kernel.org, linux-arm-msm@...r.kernel.org, imx@...ts.linux.dev, 
 devicetree@...r.kernel.org, NXP S32 Linux Team <s32@....com>, 
 0x1207@...il.com, fancer.lancer@...il.com, 
 "Jan Petrous (OSS)" <jan.petrous@....nxp.com>, 
 Jacob Keller <jacob.e.keller@...el.com>
Subject: [PATCH net-next v8 01/15] net: stmmac: Fix CSR divider comment

From: "Jan Petrous (OSS)" <jan.petrous@....nxp.com>

The comment in declaration of STMMAC_CSR_250_300M
incorrectly describes the constant as '/* MDC = clk_scr_i/122 */'
but the DWC Ether QOS Handbook version 5.20a says it is
CSR clock/124.

Signed-off-by: Jan Petrous (OSS) <jan.petrous@....nxp.com>
Reviewed-by: Jacob Keller <jacob.e.keller@...el.com>
---
 include/linux/stmmac.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index d79ff252cfdc..75cbfb576358 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -33,7 +33,7 @@
 #define	STMMAC_CSR_20_35M	0x2	/* MDC = clk_scr_i/16 */
 #define	STMMAC_CSR_35_60M	0x3	/* MDC = clk_scr_i/26 */
 #define	STMMAC_CSR_150_250M	0x4	/* MDC = clk_scr_i/102 */
-#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/122 */
+#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/124 */

 /* MTL algorithms identifiers */
 #define MTL_TX_ALGORITHM_WRR	0x0

-- 
2.47.0