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Message-ID: <45643708-c138-4c77-85ce-fa7d49f2aa72@oss.qualcomm.com>
Date: Thu, 5 Dec 2024 22:36:11 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Yongxing Mou <quic_yongmou@...cinc.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Ritesh Kumar <quic_riteshk@...cinc.com>
Subject: Re: [PATCH 1/2] arm64: dts: qcom: qcs8300: add DisplayPort device
 nodes

On 27.11.2024 11:45 AM, Yongxing Mou wrote:
> Add device tree nodes for the DPTX0 controller with their
> corresponding PHYs found on Qualcomm QCS8300 SoC.
> 
> Signed-off-by: Yongxing Mou <quic_yongmou@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 115 +++++++++++++++++++++++++++++++++-
>  1 file changed, 114 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 1642e2863affd5af0b4f68118a47b7a74b76df95..28deba0a389641b4dddbf4505d6f44c6607aa03b 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -987,6 +987,19 @@ mdss_mdp: display-controller@...1000 {
>  				interrupt-parent = <&mdss>;
>  				interrupts = <0>;
>  
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						dpu_intf0_out: endpoint {
> +							remote-endpoint = <&mdss_dp0_in>;
> +						};
> +					};
> +				};
> +
>  				mdp_opp_table: opp-table {
>  					compatible = "operating-points-v2";
>  
> @@ -1011,6 +1024,104 @@ opp-650000000 {
>  					};
>  				};
>  			};
> +
> +			mdss_dp0_phy: phy@...2a00 {
> +				compatible = "qcom,qcs8300-edp-phy";
> +
> +				reg = <0x0 0x0aec2a00 0x0 0x200>,

0x19c

> +				      <0x0 0x0aec2200 0x0 0xd0>,

0xec
> +				      <0x0 0x0aec2600 0x0 0xd0>,

0xec

For lengths

> +				      <0x0 0x0aec2000 0x0 0x1c8>;

This one's correct

> +
> +				clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> +					 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
> +				clock-names = "aux",
> +					      "cfg_ahb";

power-domains = <&rpmhpd RPMHPD_MX>;

(or maybe even MXC?)

> +
> +				#clock-cells = <1>;
> +				#phy-cells = <0>;
> +
> +				status = "disabled";
> +			};
> +
> +			mdss_dp0: displayport-controller@...4000 {
> +				compatible = "qcom,qcs8300-dp";
> +
> +				reg = <0x0 0x0af54000 0x0 0x104>,
0x200

> +				      <0x0 0x0af54200 0x0 0x0c0>,
0x200

> +				      <0x0 0x0af55000 0x0 0x770>,
0xc00

> +				      <0x0 0x0af56000 0x0 0x09c>;
0x400

for lengths

Konrad

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