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Message-Id: <20241205-v6-12-topic-socfpga-agilex5-v3-4-2a8cdf73f50a@pengutronix.de>
Date: Thu, 05 Dec 2024 10:06:04 +0100
From: Steffen Trumtrar <s.trumtrar@...gutronix.de>
To: Dinh Nguyen <dinguyen@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Richard Cochran <richardcochran@...il.com>, 
 Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 netdev@...r.kernel.org, linux-clk@...r.kernel.org, kernel@...gutronix.de, 
 Steffen Trumtrar <s.trumtrar@...gutronix.de>, 
 Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v3 4/6] arm64: dts: agilex5: add gpio0

gpio0 is the same as gpio1 with a different base address.

Signed-off-by: Steffen Trumtrar <s.trumtrar@...gutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 0035caef5af2774083885cf2d0d8a38ee8be9627..47f49d1e1442f66d97a323cd382f3f42d34ab835 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -312,6 +312,25 @@ i3c1: i3c@...a1000 {
 			status = "disabled";
 		};
 
+		gpio0: gpio@...03200 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x10c03200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&rst GPIO0_RESET>;
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <24>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		gpio1: gpio@...03300 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x10c03300 0x100>;

-- 
2.46.0


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