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Message-ID: <ec73fe36-978b-4e3a-a5de-5aafb54af9a8@redhat.com>
Date: Thu, 5 Dec 2024 10:47:21 +0100
From: Paolo Abeni <pabeni@...hat.com>
To: Divya Koppera <divya.koppera@...rochip.com>, andrew@...n.ch,
arun.ramadoss@...rochip.com, UNGLinuxDriver@...rochip.com,
hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
edumazet@...gle.com, kuba@...nel.org, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, richardcochran@...il.com,
vadim.fedorenko@...ux.dev
Subject: Re: [PATCH net-next v5 2/5] net: phy: microchip_ptp : Add ptp library
for Microchip phys
On 12/3/24 09:52, Divya Koppera wrote:
> +struct mchp_ptp_clock *mchp_ptp_probe(struct phy_device *phydev, u8 mmd,
> + u16 clk_base_addr, u16 port_base_addr)
> +{
> + struct mchp_ptp_clock *clock;
> + int rc;
> +
> + clock = devm_kzalloc(&phydev->mdio.dev, sizeof(*clock), GFP_KERNEL);
> + if (!clock)
> + return ERR_PTR(-ENOMEM);
> +
> + clock->port_base_addr = port_base_addr;
> + clock->clk_base_addr = clk_base_addr;
> + clock->mmd = mmd;
> +
> + /* Register PTP clock */
> + clock->caps.owner = THIS_MODULE;
> + snprintf(clock->caps.name, 30, "%s", phydev->drv->name);
> + clock->caps.max_adj = MCHP_PTP_MAX_ADJ;
> + clock->caps.n_ext_ts = 0;
> + clock->caps.pps = 0;
> + clock->caps.adjfine = mchp_ptp_ltc_adjfine;
> + clock->caps.adjtime = mchp_ptp_ltc_adjtime;
> + clock->caps.gettime64 = mchp_ptp_ltc_gettime64;
> + clock->caps.settime64 = mchp_ptp_ltc_settime64;
> + clock->ptp_clock = ptp_clock_register(&clock->caps,
> + &phydev->mdio.dev);
> + if (IS_ERR(clock->ptp_clock))
> + return ERR_PTR(-EINVAL);
> +
> + /* Initialize the SW */
> + skb_queue_head_init(&clock->tx_queue);
> + skb_queue_head_init(&clock->rx_queue);
> + INIT_LIST_HEAD(&clock->rx_ts_list);
> + spin_lock_init(&clock->rx_ts_lock);
> + mutex_init(&clock->ptp_lock);
The s/w initialization is completed after successfully registering the
new ptp clock, is that safe? It looks like it may race with ptp callbacks.
Cheers,
Paolo
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