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Message-Id: <20241205103729.14798-2-luxu.kernel@bytedance.com>
Date: Thu, 5 Dec 2024 18:37:09 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
ardb@...nel.org,
anup@...infault.org,
atishp@...shpatra.org
Cc: xieyongji@...edance.com,
lihangjing@...edance.com,
punit.agrawal@...edance.com,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
Xu Lu <luxu.kernel@...edance.com>
Subject: [RFC PATCH v2 01/21] riscv: mm: Distinguish hardware base page and software base page
The key idea to implement larger base page based on MMU that only
supports 4K page is to decouple the MMU page from the software page in
view of kernel mm. In contrary to software page, we denote the MMU page
as hardware page.
To decouple these two kinds of pages, we should manage, allocate and map
memory at a granularity of software page, which is exactly what existing
mm code does. The page table operations, however, should configure page
table entries at a granularity of hardware page, which is the
responsibility of arch code.
This commit introduces the concept of hardware base page for RISCV.
Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
---
arch/riscv/Kconfig | 10 ++++++++++
arch/riscv/include/asm/page.h | 7 +++++++
arch/riscv/include/asm/pgtable-32.h | 5 +++--
arch/riscv/include/asm/pgtable-64.h | 5 +++--
arch/riscv/include/asm/pgtable-bits.h | 3 ++-
arch/riscv/include/asm/pgtable.h | 1 +
6 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa8f2da87a0a..2c0cb175a92a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -289,6 +289,16 @@ config PAGE_OFFSET
default 0xc0000000 if 32BIT
default 0xff60000000000000 if 64BIT
+config RISCV_HW_PAGE_SHIFT
+ int
+ default 12
+
+config RISCV_USE_SW_PAGE
+ bool
+ depends on 64BIT
+ depends on RISCV_HW_PAGE_SHIFT != PAGE_SHIFT
+ default n
+
config KASAN_SHADOW_OFFSET
hex
depends on KASAN_GENERIC
diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 32d308a3355f..7c581a3e057b 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -12,6 +12,10 @@
#include <linux/pfn.h>
#include <linux/const.h>
+#define HW_PAGE_SHIFT CONFIG_RISCV_HW_PAGE_SHIFT
+#define HW_PAGE_SIZE (_AC(1, UL) << HW_PAGE_SHIFT)
+#define HW_PAGE_MASK (~(HW_PAGE_SIZE - 1))
+
#define PAGE_SHIFT CONFIG_PAGE_SHIFT
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE - 1))
@@ -185,6 +189,9 @@ extern phys_addr_t __phys_addr_symbol(unsigned long x);
#define __pa(x) __virt_to_phys((unsigned long)(x))
#define __va(x) ((void *)__pa_to_va_nodebug((phys_addr_t)(x)))
+#define pfn_to_hwpfn(pfn) (pfn << (PAGE_SHIFT - HW_PAGE_SHIFT))
+#define hwpfn_to_pfn(hwpfn) (hwpfn >> (PAGE_SHIFT - HW_PAGE_SHIFT))
+
#define phys_to_pfn(phys) (PFN_DOWN(phys))
#define pfn_to_phys(pfn) (PFN_PHYS(pfn))
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 00f3369570a8..159a668c3dd8 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -20,9 +20,10 @@
/*
* rv32 PTE format:
* | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- * PFN reserved for SW D A G U X W R V
+ * HW_PFN reserved for SW D A G U X W R V
*/
-#define _PAGE_PFN_MASK GENMASK(31, 10)
+#define _PAGE_HW_PFN_MASK GENMASK(31, 10)
+#define _PAGE_PFN_MASK GENMASK(31, (10 + PAGE_SHIFT - HW_PAGE_SHIFT))
#define _PAGE_NOCACHE 0
#define _PAGE_IO 0
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 0897dd99ab8d..963aa4be9eed 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -72,9 +72,10 @@ typedef struct {
/*
* rv64 PTE format:
* | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- * N MT RSV PFN reserved for SW D A G U X W R V
+ * N MT RSV HW_PFN reserved for SW D A G U X W R V
*/
-#define _PAGE_PFN_MASK GENMASK(53, 10)
+#define _PAGE_HW_PFN_MASK GENMASK(53, 10)
+#define _PAGE_PFN_MASK GENMASK(53, (10 + PAGE_SHIFT - HW_PAGE_SHIFT))
/*
* [63] Svnapot definitions:
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index a8f5205cea54..e5bb6a805505 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -31,7 +31,8 @@
/* Used for swap PTEs only. */
#define _PAGE_SWP_EXCLUSIVE _PAGE_ACCESSED
-#define _PAGE_PFN_SHIFT 10
+#define _PAGE_HWPFN_SHIFT 10
+#define _PAGE_PFN_SHIFT (_PAGE_HWPFN_SHIFT + (PAGE_SHIFT - HW_PAGE_SHIFT))
/*
* when all of R/W/X are zero, the PTE is a pointer to the next level
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index e79f15293492..9d6d0ff86c76 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -114,6 +114,7 @@
#include <linux/mm_types.h>
#include <asm/compat.h>
+#define __page_val_to_hwpfn(_val) (((_val) & _PAGE_HW_PFN_MASK) >> _PAGE_HWPFN_SHIFT)
#define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT)
#ifdef CONFIG_64BIT
--
2.20.1
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