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Message-ID:
 <TY3PR01MB11346B32E8CA9C0E4E677C09A86302@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Thu, 5 Dec 2024 12:19:11 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Liu Ying
	<victor.liu@....com>
CC: "tomm.merciai@...il.com" <tomm.merciai@...il.com>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>, Tommaso
 Merciai <tommaso.merciai.xr@...renesas.com>, Andrzej Hajda
	<andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>, Robert
 Foss <rfoss@...nel.org>, laurent.pinchart
	<laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>, Jernej
 Skrabec <jernej.skrabec@...il.com>, Maarten Lankhorst
	<maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
	Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>,
	Simona Vetter <simona@...ll.ch>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] drm/bridge: ite-it6263: Support VESA input format

Hi Dmitry Baryshkov,

> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Sent: 05 December 2024 11:43
> Subject: Re: [PATCH] drm/bridge: ite-it6263: Support VESA input format
> 
> On Thu, 5 Dec 2024 at 11:01, Liu Ying <victor.liu@....com> wrote:
> >
> > On 12/04/2024, Biju Das wrote:
> > > Hi Liu Ying,
> >
> > Hi Biju,
> >
> > >
> > >> -----Original Message-----
> > >> From: Liu Ying <victor.liu@....com>
> > >> Sent: 04 December 2024 03:43
> > >> Subject: Re: [PATCH] drm/bridge: ite-it6263: Support VESA input
> > >> format
> > >>
> > >> On 12/04/2024, Dmitry Baryshkov wrote:
> > >>> On Tue, Dec 03, 2024 at 06:21:29PM +0100, tomm.merciai@...il.com wrote:
> > >>>> From: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
> > >>>>
> > >>>> Introduce it6263_is_input_bus_fmt_valid() and refactor the
> > >>>> it6263_bridge_atomic_get_input_bus_fmts() function to support
> > >>>> VESA format by selecting the LVDS input format based on the LVDS
> > >>>> data mapping and thereby support both JEIDA and VESA input formats.
> > >>>
> > >>> For the patch itself,
> > >>>
> > >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> > >>>
> > >>> A more generic question: is the bridge limited to 4 lanes or does
> > >>> it support 3-lane or 5-lane configurations?
> > >>
> > >> According to ite,it6263.yaml, the bridge supports all the data
> > >> mappings(jeida-{18,24,30} and vesa-
> > >> {24,30}) listed in lvds-data-mapping.yaml.  lvds-data-mapping.yaml
> > >> specifies the data lanes(3/4/5) used by each of the data mappings.  So, the bridge supports 3, 4
> or 5 data lanes.
> > >
> > > In Renesas SMARC RZ/G3E LVDS add on board, only 4 LVDS Rx lanes connected. The 5th one is
> unconnected.
> > > What is the situation in your board Liu Ying?
> >
> > The adapter cards I'm using to connect with i.MX8MP EVK have only 4
> > LVDS data lanes routed out.
> 
> What about the bridge SoC. I don't understand why the driver gets limited by a particular add-on card.

Bridge SoC supports up to 5 Rx Lanes. But vendors do the wiring to bridge SoC and 
currently as far as we know there are 2 boards with ITE 6263 bridge SoC and both of
them has 4 LVDS rx lanes connected and both vesa-24 and Jeida-24 formats are tested.

Cheers,
Biju


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