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Message-ID: <20241206152207.37928-2-antoniu.miclaus@analog.com>
Date: Fri, 6 Dec 2024 17:22:05 +0200
From: Antoniu Miclaus <antoniu.miclaus@...log.com>
To: <jic23@...nel.org>, <robh@...nel.org>, <conor+dt@...nel.org>,
<linux-iio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pwm@...r.kernel.org>
CC: Antoniu Miclaus <antoniu.miclaus@...log.com>
Subject: [PATCH 2/3] iio: frequency: adf4371: add differential ref
Add support for differential input reference clock.
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@...log.com>
---
drivers/iio/frequency/adf4371.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c
index b27088464826..55bee06fb42d 100644
--- a/drivers/iio/frequency/adf4371.c
+++ b/drivers/iio/frequency/adf4371.c
@@ -41,6 +41,10 @@
#define ADF4371_MOD2WORD_MSK GENMASK(5, 0)
#define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
+/* ADF4371_REG22 */
+#define ADF4371_REFIN_MODE_MASK BIT(6)
+#define ADF4371_REFIN_MODE(x) FIELD_PREP(ADF4371_REFIN_MODE_MASK, x)
+
/* ADF4371_REG24 */
#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)
#define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)
@@ -69,6 +73,7 @@
#define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
#define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
+#define ADF4371_MAX_FREQ_REFIN_SE 500000000UL /* Hz */
/* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
#define ADF4371_MODULUS1 33554432ULL
@@ -476,6 +481,7 @@ static int adf4371_setup(struct adf4371_state *st)
{
unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
unsigned int vco_band_div, tmp;
+ bool ref_diff_en;
int ret;
/* Perform a software reset */
@@ -497,12 +503,25 @@ static int adf4371_setup(struct adf4371_state *st)
return ret;
}
+ ref_diff_en = device_property_read_bool(&st->spi->dev, "adi,ref-differential-enable");
+
/* Set address in ascending order, so the bulk_write() will work */
ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1));
if (ret < 0)
return ret;
+
+ if ((ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN) ||
+ (!ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN_SE))
+ return -EINVAL;
+
+ ret = regmap_update_bits(st->regmap, ADF4371_REG(0x22),
+ ADF4371_REFIN_MODE_MASK,
+ ADF4371_REFIN_MODE(ref_diff_en));
+ if (ret < 0)
+ return ret;
+
/*
* Calculate and maximize PFD frequency
* fPFD = REFIN × ((1 + D)/(R × (1 + T)))
--
2.47.1
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