linux-kernel - [tip: x86/urgent] x86/CPU/AMD: WARN when setting EFER.AUTOIBRS if and only if the WRMSR fails

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Message-ID: <173351175403.412.3888951416121519088.tip-bot2@tip-bot2>
Date: Fri, 06 Dec 2024 19:02:34 -0000
From: "tip-bot2 for Sean Christopherson" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Nathan Chancellor <nathan@...nel.org>,
 Sean Christopherson <seanjc@...gle.com>, Ingo Molnar <mingo@...nel.org>,
 x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: x86/urgent] x86/CPU/AMD: WARN when setting EFER.AUTOIBRS if and
 only if the WRMSR fails

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     492077668fb453b8b16c842fcf3fafc2ebc190e9
Gitweb:        https://git.kernel.org/tip/492077668fb453b8b16c842fcf3fafc2ebc190e9
Author:        Sean Christopherson <seanjc@...gle.com>
AuthorDate:    Fri, 06 Dec 2024 08:20:06 -08:00
Committer:     Ingo Molnar <mingo@...nel.org>
CommitterDate: Fri, 06 Dec 2024 19:57:05 +01:00

x86/CPU/AMD: WARN when setting EFER.AUTOIBRS if and only if the WRMSR fails

When ensuring EFER.AUTOIBRS is set, WARN only on a negative return code
from msr_set_bit(), as '1' is used to indicate the WRMSR was successful
('0' indicates the MSR bit was already set).

Fixes: 8cc68c9c9e92 ("x86/CPU/AMD: Make sure EFER[AIBRSE] is set")
Reported-by: Nathan Chancellor <nathan@...nel.org>
Signed-off-by: Sean Christopherson <seanjc@...gle.com>
Signed-off-by: Ingo Molnar <mingo@...nel.org>
Link: https://lore.kernel.org/r/Z1MkNofJjt7Oq0G6@google.com
Closes: https://lore.kernel.org/all/20241205220604.GA2054199@thelio-3990X
---
 arch/x86/kernel/cpu/amd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index d8408aa..79d2e17 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1065,7 +1065,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	 */
 	if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
-		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
+		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0);
 
 	/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
 	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);