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Message-ID:
<TY3PR01MB1134653DFB1CEB5D81F357B1A86322@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Sat, 7 Dec 2024 10:36:01 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: John Madieu <john.madieu.xa@...renesas.com>, Geert Uytterhoeven
<geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>, Rob Herring
<robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
CC: "john.madieu@...il.com" <john.madieu@...il.com>,
"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, John Madieu
<john.madieu.xa@...renesas.com>
Subject: RE: [PATCH 3/5] soc: renesas: rz-sysc: Add support for RZ/G3E family
Hi John,
Thanks for the patch.
> -----Original Message-----
> From: John Madieu <john.madieu.xa@...renesas.com>
> Sent: 06 December 2024 21:26
> Subject: [PATCH 3/5] soc: renesas: rz-sysc: Add support for RZ/G3E family
>
> Add SoC detection support for RZ/G3E SoC. Also add support for detecting the number of cores and
> ETHOS-U55 NPU and also detect PLL mismatch for SW settings other than 1.7GHz.
>
> Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
> ---
> drivers/soc/renesas/Kconfig | 6 +++
> drivers/soc/renesas/Makefile | 1 +
> drivers/soc/renesas/r9a09g047-sysc.c | 70 ++++++++++++++++++++++++++++
> drivers/soc/renesas/rz-sysc.c | 44 +++++++++++------
> drivers/soc/renesas/rz-sysc.h | 7 +++
> 5 files changed, 114 insertions(+), 14 deletions(-) create mode 100644
> drivers/soc/renesas/r9a09g047-sysc.c
>
> diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index
> a792a3e915fe..9e46b0ee6e80 100644
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -348,6 +348,7 @@ config ARCH_R9A09G011
>
> config ARCH_R9A09G047
> bool "ARM64 Platform support for RZ/G3E"
> + select SYSC_R9A09G047
> help
> This enables support for the Renesas RZ/G3E SoC variants.
>
> @@ -386,9 +387,14 @@ config RST_RCAR
>
> config SYSC_RZ
> bool "System controller for RZ SoCs" if COMPILE_TEST
> + depends on MFD_SYSCON
>
> config SYSC_R9A08G045
> bool "Renesas RZ/G3S System controller support" if COMPILE_TEST
> select SYSC_RZ
>
> +config SYSC_R9A09G047
> + bool "Renesas RZ/G3E System controller support" if COMPILE_TEST
> + select SYSC_RZ
> +
> endif # SOC_RENESAS
> diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index
> 8cd139b3dd0a..3256706112d9 100644
> --- a/drivers/soc/renesas/Makefile
> +++ b/drivers/soc/renesas/Makefile
> @@ -7,6 +7,7 @@ ifdef CONFIG_SMP
> obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
> endif
> obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o
> +obj-$(CONFIG_SYSC_R9A09G047) += r9a09g047-sysc.o
>
> # Family
> obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o
> diff --git a/drivers/soc/renesas/r9a09g047-sysc.c b/drivers/soc/renesas/r9a09g047-sysc.c
> new file mode 100644
> index 000000000000..32bdab9f1774
> --- /dev/null
> +++ b/drivers/soc/renesas/r9a09g047-sysc.c
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RZ/G3E System controller driver
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +
> +#include "rz-sysc.h"
> +
> +/* Register definitions */
> +#define SYS_LSI_DEVID 0x304
> +#define SYS_LSI_MODE 0x300
> +#define SYS_LSI_PRR 0x308
> +#define SYS_LSI_DEVID_REV GENMASK(31, 28)
> +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0)
> +#define SYS_LSI_PRR_CA55_DIS BIT(8)
> +#define SYS_LSI_PRR_NPU_DIS BIT(1)
> +/*
> + * BOOTPLLCA[1:0]
> + * [0,0] => 1.1GHZ
> + * [0,1] => 1.5GHZ
> + * [1,0] => 1.6GHZ
> + * [1,1] => 1.7GHZ
> + */
> +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
> +#define SYS_LSI_MODE_CA55_1_7GHz 0x3
> +
> +static void rzg3e_extended_device_identification(struct device *dev,
> + void __iomem *sysc_base,
> + struct soc_device_attribute *soc_dev_attr) {
> + u32 prr_val, mode_val;
> + bool is_quad_core, npu_enabled;
> +
> + prr_val = readl(sysc_base + SYS_LSI_PRR);
> + mode_val = readl(sysc_base + SYS_LSI_MODE);
> +
> + /* Check CPU and NPU configuration */
> + is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
> + npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
> +
> + dev_info(dev, "Detected Renesas %s Core %s %s Rev %s %s\n",
> + is_quad_core ? "Quad" : "Dual",
> + soc_dev_attr->family,
> + soc_dev_attr->soc_id,
> + soc_dev_attr->revision,
> + npu_enabled ? "with Ethos-U55" : "");
> +
> + /* Check CA55 PLL configuration */
> + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHz)
> + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); }
> +
> +static const struct rz_sysc_soc_id_init_data rzg3e_sysc_soc_id_init_data __initconst = {
> + .family = "RZ/G3E",
> + .id = 0x8679447,
> + .offset = SYS_LSI_DEVID,
> + .revision_mask = SYS_LSI_DEVID_REV,
> + .specific_id_mask = SYS_LSI_DEVID_SPECIFIC,
> + .extended_device_identification =
> +rzg3e_extended_device_identification,
> +};
> +
> +const struct rz_sysc_init_data rzg3e_sysc_init_data = {
> + .soc_id_init_data = &rzg3e_sysc_soc_id_init_data, };
> diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index
> d34d295831b8..515eca249b6e 100644
> --- a/drivers/soc/renesas/rz-sysc.c
> +++ b/drivers/soc/renesas/rz-sysc.c
> @@ -231,7 +231,7 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat
>
> soc_id_start = strchr(match->compatible, ',') + 1;
> soc_id_end = strchr(match->compatible, '-');
> - size = soc_id_end - soc_id_start;
> + size = soc_id_end - soc_id_start + 1;
> if (size > 32)
> size = 32;
> strscpy(soc_id, soc_id_start, size);
> @@ -257,8 +257,16 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *mat
> return -ENODEV;
> }
>
> - dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family,
> - soc_dev_attr->soc_id, soc_dev_attr->revision);
> + /* Try to call SoC-specific device identification */
> + if (soc_data->extended_device_identification) {
> + soc_data->extended_device_identification(sysc->dev, sysc->base,
> + soc_dev_attr);
> + } else {
> + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n",
> + soc_dev_attr->family,
> + soc_dev_attr->soc_id,
> + soc_dev_attr->revision);
> + }
>
> soc_dev = soc_device_register(soc_dev_attr);
> if (IS_ERR(soc_dev))
> @@ -283,6 +291,9 @@ static struct regmap_config rz_sysc_regmap = { static const struct of_device_id
> rz_sysc_match[] = { #ifdef CONFIG_SYSC_R9A08G045
> { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data },
> +#endif
> +#ifdef CONFIG_SYSC_R9A09G047
> + { .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sysc_init_data
> +},
> #endif
> { }
> };
> @@ -315,20 +326,25 @@ static int rz_sysc_probe(struct platform_device *pdev)
> return ret;
>
> data = match->data;
> - if (!data->max_register_offset)
> - return -EINVAL;
> + if (data->signals_init_data) {
> + if (!data->max_register_offset)
> + return -EINVAL;
I assume you don't have any signal use case like RZ/G3S.
Can you please confirm is it correct for RZ/G3E?
Multiple drivers/devices accessing same register like USB PWRRDY register in RZ/G3S?
Cheers,
Biju
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