lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1f597801-62b7-4fb1-9ffe-1b9554c4e23c@ieee.org>
Date: Sat, 7 Dec 2024 10:50:01 -0600
From: Alex Elder <elder@...e.org>
To: Zhang Zekun <zhangzekun11@...wei.com>, xuwei5@...ilicon.com,
 lihuisong@...wei.com, Jonathan.Cameron@...wei.com
Cc: linux-kernel@...r.kernel.org, liuyongqiang13@...wei.com
Subject: Re: [PATCH 0/2] soc: hisilicon: Add power control support for kunpeng
 HBM

On 12/6/24 5:28 AM, Zhang Zekun wrote:
> Add power control support for High Bandwidth Memory (HBM) for Kunpeng SoC
> platform. HBM devices on Kunpeng SoC can provide higher bandwidth at the
> cost of higher power consumption. Providing power control methods can help
> reducing the power when the workload does not need use HBM.

Could you explain a little more here how HBM is represented in the
system?  When it's powered on, it seems like it's "just memory".
And what you're doing here is enabling a power optimization to
allow this type of memory to be powered off when not in use.
How do you know whether it is in use?  What entity is meant to
be able to power this memory on and off?

In addition, it looks like there can be more than one instance of
an HBM device, and each is available to be used only for certain
CPUs.  Can you provide more information about that sort of
architectural detail?

Finally, the second patch enables "cache" functionality.  Maybe
this is something defined by ACPI and is well understood by others
but it's not clear to me what this even means.  How is an HBM
used, and how does its cache enabled/disabled state interact
with the device enabled/disabled state?

Is an HBM device something completely different from an HBM cache
device?  I guess I just lack a big-picture overview of how this
HBM fits into a system.

					-Alex

> 
> Zhang Zekun (2):
>    soc: hisilicon: kunpeng_hbmdev: Add support for controling the power
>      of hbm memory
>    soc: hisilicon: kunpeng_hbmcache: Add support for online and offline
>      the hbm cache
> 
>   MAINTAINERS                              |   7 +
>   drivers/soc/hisilicon/Kconfig            |  23 +++
>   drivers/soc/hisilicon/Makefile           |   2 +
>   drivers/soc/hisilicon/kunpeng_hbm.h      |  31 ++++
>   drivers/soc/hisilicon/kunpeng_hbmcache.c | 136 +++++++++++++++
>   drivers/soc/hisilicon/kunpeng_hbmdev.c   | 210 +++++++++++++++++++++++
>   6 files changed, 409 insertions(+)
>   create mode 100644 drivers/soc/hisilicon/kunpeng_hbm.h
>   create mode 100644 drivers/soc/hisilicon/kunpeng_hbmcache.c
>   create mode 100644 drivers/soc/hisilicon/kunpeng_hbmdev.c
> 


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ