| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <9fbbf3d1-9543-42f8-a80c-1527811109ef@tuxon.dev>
Date: Sun, 8 Dec 2024 18:29:55 +0200
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, nicolas.ferre@...rochip.com,
alexandre.belloni@...tlin.com, mturquette@...libre.com, sboyd@...nel.org,
arnd@...db.de
Cc: dharma.b@...rochip.com, mihai.sain@...rochip.com,
romain.sioen@...rochip.com, varshini.rajendran@...rochip.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-spi@...r.kernel.org,
linux-serial@...r.kernel.org
Subject: Re: [PATCH v3 09/13] ARM: dts: microchip: add sama7d65 SoC DT
On 08.12.2024 18:28, Claudiu Beznea wrote:
>
>
> On 06.12.2024 21:59, Ryan.Wanner@...rochip.com wrote:
>> From: Ryan Wanner <Ryan.Wanner@...rochip.com>
>>
>> Add Device Tree for sama7d65 SoC.
>>
>> Co-developed-by: Dharma Balasubiramani <dharma.b@...rochip.com>
>> Signed-off-by: Dharma Balasubiramani <dharma.b@...rochip.com>
>> Co-developed-by: Romain Sioen <romain.sioen@...rochip.com>
>> Signed-off-by: Romain Sioen <romain.sioen@...rochip.com>
>> Co-developed-by: Varshini Rajendran <varshini.rajendran@...rochip.com>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@...rochip.com>
>> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
>> ---
>> arch/arm/boot/dts/microchip/sama7d65.dtsi | 145 ++++++++++++++++++++++
>> 1 file changed, 145 insertions(+)
>> create mode 100644 arch/arm/boot/dts/microchip/sama7d65.dtsi
>>
>> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
>> new file mode 100644
>> index 000000000000..0dcd80690210
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
>> @@ -0,0 +1,145 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC
>> + *
>> + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries
>> + *
>> + * Author: Ryan Wanner <Ryan.Wanner@...rochip.com>
>> + *
>> + */
>> +
>> +#include <dt-bindings/clock/at91.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/mfd/at91-usart.h>
>> +
>> +/ {
>> + model = "Microchip SAMA7D65 family SoC";
>> + compatible = "microchip,sama7d65";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-parent = <&gic>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + reg = <0x0>;
>> + device_type = "cpu";
>> + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
>> + clock-names = "cpu";
>> + };
>> + };
>> +
>> + clocks {
>> + main_xtal: clock-mainxtal {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + slow_xtal: clock-slowxtal {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + ranges;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + pioa: pinctrl@...14000 {
>> + compatible = "microchip,sama7d65-pinctrl";
>> + reg = <0xe0014000 0x800>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +
>> + pmc: clock-controller@...18000 {
>> + compatible = "microchip,sama7d65-pmc", "syscon";
>> + reg = <0xe0018000 0x200>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + #clock-cells = <2>;
>> + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
>> + clock-names = "td_slck", "md_slck", "main_xtal";
>> + };
>> +
>> + clk32k: clock-controller@...1d500 {
>> + compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
>> + reg = <0xe001d500 0x4>;
>> + clocks = <&slow_xtal>;
>> + #clock-cells = <1>;
>> + };
>> +
>> + sdmmc1: mmc@...08000 {
>> + compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
>> + reg = <0xe1208000 0x400>;
>> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>;
>> + clock-names = "hclock", "multclk";
>> + assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
>> + assigned-clock-rates = <200000000>;
>> + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
>> + status = "disabled";
>> + };
>> +
>> + pit64b0: timer@...00000 {
>> + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
>> + reg = <0xe1800000 0x100>;
>> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
>> + clock-names = "pclk", "gclk";
>> + };
>> +
>> + pit64b1: timer@...04000 {
>> + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
>> + reg = <0xe1804000 0x100>;
>> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>;
>> + clock-names = "pclk", "gclk";
>> + };
>> +
>> + flx6: flexcom@...20000 {
>> + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
>> + reg = <0xe2020000 0x200>;
>> + ranges = <0x0 0xe2020000 0x800>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
>> + status = "disabled";
>> +
>> + uart6: serial@200 {
>> + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
>> + reg = <0x200 0x200>;
>> + atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
>
> Vendor specific props would be at the end, before states, according to [1].
> I'll adjust it while applying.
>
> [1]
This is the link, sorry:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n122
Other than that:
Reviewed-by: Claudiu Beznea <claudiu.beznea@...on.dev>
Powered by blists - more mailing lists