linux-kernel - Re: [PATCH v3 08/13] clk: at91: sama7d65: add sama7d65 pmc driver

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Message-ID: <c0206c74-33d3-4715-9a01-256394919fc8@wanadoo.fr>
Date: Sun, 8 Dec 2024 17:35:56 +0100
From: Christophe JAILLET <christophe.jaillet@...adoo.fr>
To: Ryan.Wanner@...rochip.com, robh@...nel.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, nicolas.ferre@...rochip.com,
 alexandre.belloni@...tlin.com, claudiu.beznea@...on.dev,
 mturquette@...libre.com, sboyd@...nel.org, arnd@...db.de
Cc: dharma.b@...rochip.com, mihai.sain@...rochip.com,
 romain.sioen@...rochip.com, varshini.rajendran@...rochip.com,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-gpio@...r.kernel.org, linux-spi@...r.kernel.org,
 linux-serial@...r.kernel.org
Subject: Re: [PATCH v3 08/13] clk: at91: sama7d65: add sama7d65 pmc driver

Le 06/12/2024 à 20:59, Ryan.Wanner@...rochip.com a écrit :
> From: Ryan Wanner <Ryan.Wanner@...rochip.com>
> 
> Add clock support for SAMA7D65 SoC.
> 
> Increase maximum number of valid master clocks. The PMC for the SAMA7D65
> requires 9 master clocks.
> 
> Increase maximum amount of PLLs to 9 to support SAMA7D65 SoC PLL
> requirements.
> 
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>

...

> +	for (i = 0; i < ARRAY_SIZE(sama7d65_gck); i++) {
> +		u8 num_parents = 4 + sama7d65_gck[i].pp_count;
> +		struct clk_hw *tmp_parent_hws[8];
> +		u32 *mux_table;
> +
> +		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
> +					  GFP_KERNEL);
> +		if (!mux_table)
> +			goto err_free;
> +
> +		PMC_INIT_TABLE(mux_table, 4);
> +		PMC_FILL_TABLE(&mux_table[4], sama7d65_gck[i].pp_mux_table,
> +			       sama7d65_gck[i].pp_count);
> +		for (j = 0; j < sama7d65_gck[i].pp_count; j++) {
> +			u8 pll_id = sama7d65_gck[i].pp[j].pll_id;
> +			u8 pll_compid = sama7d65_gck[i].pp[j].pll_compid;
> +
> +			tmp_parent_hws[j] = sama7d65_plls[pll_id][pll_compid].hw;
> +		}
> +		PMC_FILL_TABLE(&parent_hws[4], tmp_parent_hws,
> +			       sama7d65_gck[i].pp_count);
> +
> +		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
> +						 &sama7d65_pcr_layout,
> +						 sama7d65_gck[i].n, NULL,
> +						 parent_hws, mux_table,
> +						 num_parents,
> +						 sama7d65_gck[i].id,
> +						 &sama7d65_gck[i].r,
> +						 sama7d65_gck[i].pp_chg_id);
> +		if (IS_ERR(hw))

If we fail here, mux_table is not freed, because it is not stored yet in 
alloc_mem.

> +			goto err_free;
> +
> +		sama7d65_pmc->ghws[sama7d65_gck[i].id] = hw;
> +		alloc_mem[alloc_mem_size++] = mux_table;
> +	}
> +
> +	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7d65_pmc);
> +	kfree(alloc_mem);
> +
> +	return;
> +
> +err_free:
> +	if (alloc_mem) {
> +		for (i = 0; i < alloc_mem_size; i++)
> +			kfree(alloc_mem[i]);
> +		kfree(alloc_mem);
> +	}
> +
> +	kfree(sama7d65_pmc);
> +}
> +
> +/* Some clks are used for a clocksource */
> +CLK_OF_DECLARE(sama7d65_pmc, "microchip,sama7d65-pmc", sama7d65_pmc_setup);

CJ