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Message-ID: <d2ce1009-15ba-44bc-9dbb-4d606fb25739@linaro.org>
Date: Mon, 9 Dec 2024 15:06:23 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Akhil P Oommen <quic_akhilpo@...cinc.com>, Rob Clark
<robdclark@...il.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v4 6/7] arm64: qcom: dts: sm8550: add interconnect and
opp-peak-kBps for GPU
On 09/12/2024 14:10, Akhil P Oommen wrote:
> On 12/9/2024 6:32 PM, Akhil P Oommen wrote:
>> On 12/5/2024 8:31 PM, Neil Armstrong wrote:
>>> Each GPU OPP requires a specific peak DDR bandwidth, let's add
>>> those to each OPP and also the related interconnect path.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>>
>> I haven't checked each bw value, still
>>
>> Reviewed-by: Akhil P Oommen <quic_akhilpo@...cinc.com>
>>
>> -Akhil
>>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> index e7774d32fb6d2288748ecec00bf525b2b3c40fbb..955f58b2cb4e4ca3fd33f1555e36a15cfc82d642 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> @@ -14,6 +14,7 @@
>>> #include <dt-bindings/firmware/qcom,scm.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/interconnect/qcom,icc.h>
>>> #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
>>> #include <dt-bindings/mailbox/qcom-ipcc.h>
>>> #include <dt-bindings/power/qcom-rpmpd.h>
>>> @@ -2114,6 +2115,10 @@ gpu: gpu@...0000 {
>>> qcom,gmu = <&gmu>;
>>> #cooling-cells = <2>;
>>>
>>> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>>> + interconnect-names = "gfx-mem";
>>> +
>>> status = "disabled";
>>>
>>> zap-shader {
>>> @@ -2127,41 +2132,49 @@ gpu_opp_table: opp-table {
>>> opp-680000000 {
>>> opp-hz = /bits/ 64 <680000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>>> + opp-peak-kBps = <16500000>;
>>> };
>>>
>>> opp-615000000 {
>>> opp-hz = /bits/ 64 <615000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
>>> + opp-peak-kBps = <16500000>;
>
> Seems like you are using value from "qcom,bus-max" node for each opp in
> downstream devicetree. Except for the highest OPP, we should use the
> value from "qcom,bus-freq" node. That is supposed to give the best perf
> per watt.
Ack, I'll switch to the qcom,bus-freq value,
Thanks,
Neil
>
> -Akhil.
>
>>> };
>>>
>>> opp-550000000 {
>>> opp-hz = /bits/ 64 <550000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>>> + opp-peak-kBps = <12449218>;
>>> };
>>>
>>> opp-475000000 {
>>> opp-hz = /bits/ 64 <475000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
>>> + opp-peak-kBps = <8171875>;
>>> };
>>>
>>> opp-401000000 {
>>> opp-hz = /bits/ 64 <401000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>>> + opp-peak-kBps = <6671875>;
>>> };
>>>
>>> opp-348000000 {
>>> opp-hz = /bits/ 64 <348000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
>>> + opp-peak-kBps = <6074218>;
>>> };
>>>
>>> opp-295000000 {
>>> opp-hz = /bits/ 64 <295000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>>> + opp-peak-kBps = <6074218>;
>>> };
>>>
>>> opp-220000000 {
>>> opp-hz = /bits/ 64 <220000000>;
>>> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
>>> + opp-peak-kBps = <6074218>;
>>> };
>>> };
>>> };
>>>
>>
>
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