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Message-Id: <b4426c4762bd778873d204a2796885ccd98d7c69.1733726572.git.unicorn_wang@outlook.com>
Date: Mon, 9 Dec 2024 15:20:30 +0800
From: Chen Wang <unicornxw@...il.com>
To: kw@...ux.com,
u.kleine-koenig@...libre.com,
aou@...s.berkeley.edu,
arnd@...db.de,
bhelgaas@...gle.com,
unicorn_wang@...look.com,
conor+dt@...nel.org,
guoren@...nel.org,
inochiama@...look.com,
krzk+dt@...nel.org,
lee@...nel.org,
lpieralisi@...nel.org,
manivannan.sadhasivam@...aro.org,
palmer@...belt.com,
paul.walmsley@...ive.com,
pbrobinson@...il.com,
robh@...nel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org,
linux-riscv@...ts.infradead.org,
chao.wei@...hgo.com,
xiaoguang.xing@...hgo.com,
fengchun.li@...hgo.com,
helgaas@...nel.org
Subject: [PATCH v2 4/5] riscv: sophgo: dts: add pcie controllers for SG2042
From: Chen Wang <unicorn_wang@...look.com>
Add PCIe controller nodes in DTS for Sophgo SG2042.
Default they are disabled.
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 89 ++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index e62ac51ac55a..bbb7cabab9de 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -195,6 +195,95 @@ clkgen: clock-controller@...0012000 {
#clock-cells = <1>;
};
+ pcie_rc0: pcie@...0000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60000000 0x0 0x02000000>,
+ <0x40 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0x3f>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ sophgo,pcie-port = <0>;
+ sophgo,syscon-pcie-ctrl = <&cdns_pcie0_ctrl>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ cdns_pcie0_ctrl: syscon@...1800000 {
+ compatible = "sophgo,sg2042-pcie-ctrl", "syscon";
+ reg = <0x70 0x61800000 0x0 0x800000>;
+ };
+
+ pcie_rc1: pcie@...2000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62000000 0x0 0x00800000>,
+ <0x48 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
+ bus-range = <0x80 0xbf>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ sophgo,pcie-port = <0>;
+ sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
+ msi-parent = <&msi_pcie>;
+ status = "disabled";
+ msi_pcie: msi {
+ compatible = "sophgo,sg2042-pcie-msi";
+ msi-controller;
+ interrupt-parent = <&intc>;
+ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ };
+ };
+
+ pcie_rc2: pcie@...2800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62800000 0x0 0x00800000>,
+ <0x4c 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>,
+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
+ bus-range = <0xc0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ sophgo,pcie-port = <1>;
+ sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ cdns_pcie1_ctrl: syscon@...3800000 {
+ compatible = "sophgo,sg2042-pcie-ctrl", "syscon";
+ reg = <0x70 0x63800000 0x0 0x800000>;
+ };
+
clint_mswi: interrupt-controller@...4000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
--
2.34.1
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