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Message-ID: <384913986510d3bb5ca198962dd5a124b9282853.camel@posteo.de>
Date: Mon, 09 Dec 2024 07:41:43 +0000
From: Martin Kepplinger <martink@...teo.de>
To: Nikolaus Voss <nv@...n.de>, Liu Ying <victor.liu@....nxp.com>
Cc: Alexander Stein <alexander.stein@...tq-group.com>, Liu Ying
<victor.liu@....com>, Luca Ceresoli <luca.ceresoli@...tlin.com>, Fabio
Estevam <festevam@...x.de>, Marek Vasut <marex@...x.de>, Andrzej Hajda
<andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>, Laurent Pinchart
<Laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie
<airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
nikolaus.voss@...g-streit.com, miquel.raynal@...tlin.com
Subject: Re: [PATCH] drm: bridge: fsl-ldb: fixup mode on freq mismatch
Am Montag, dem 02.12.2024 um 11:13 +0100 schrieb Nikolaus Voss:
> Hi Liu,
>
> On 02.12.2024 07:32, Liu Ying wrote:
> > On 11/27/2024, Nikolaus Voss wrote:
> > > LDB clock has to be a fixed multiple of the pixel clock.
> > > As LDB and pixel clock are derived from different clock sources
> > > (at least on imx8mp), this constraint cannot be satisfied for
> > > any pixel clock, which leads to flickering and incomplete
> > > lines on the attached display.
> > >
> > > To overcome this, check this condition in mode_fixup() and
> > > adapt the pixel clock accordingly.
> > >
> > > Cc: <stable@...r.kernel.org>
> >
> > It looks like stable is not effectively Cc'ed.
> > Need a Fixes tag?
>
> I will include
> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale
> i.MX8MP LDB bridge")
> in v2.
>
> >
> > >
> > > Signed-off-by: Nikolaus Voss <nv@...n.de>
> > > ---
> > > drivers/gpu/drm/bridge/fsl-ldb.c | 40
> > > ++++++++++++++++++++++++++++----
> > > 1 file changed, 36 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c
> > > b/drivers/gpu/drm/bridge/fsl-ldb.c
> > > index 0e4bac7dd04ff..e341341b8c600 100644
> > > --- a/drivers/gpu/drm/bridge/fsl-ldb.c
> > > +++ b/drivers/gpu/drm/bridge/fsl-ldb.c
> > > @@ -104,12 +104,14 @@ static inline struct fsl_ldb
> > > *to_fsl_ldb(struct
> > > drm_bridge *bridge)
> > > return container_of(bridge, struct fsl_ldb, bridge);
> > > }
> > >
> > > +static unsigned int fsl_ldb_link_freq_factor(const struct
> > > fsl_ldb
> > > *fsl_ldb)
> > > +{
> > > + return fsl_ldb_is_dual(fsl_ldb) ? 3500 : 7000;
> > > +}
> > > +
> > > static unsigned long fsl_ldb_link_frequency(struct fsl_ldb
> > > *fsl_ldb,
> > > int clock)
> > > {
> > > - if (fsl_ldb_is_dual(fsl_ldb))
> > > - return clock * 3500;
> > > - else
> > > - return clock * 7000;
> > > + return clock * fsl_ldb_link_freq_factor(fsl_ldb);
> > > }
> > >
> > > static int fsl_ldb_attach(struct drm_bridge *bridge,
> > > @@ -121,6 +123,35 @@ static int fsl_ldb_attach(struct drm_bridge
> > > *bridge,
> > > bridge, flags);
> > > }
> > >
> > > +static bool fsl_ldb_mode_fixup(struct drm_bridge *bridge,
> > > + const struct drm_display_mode
> > > *mode,
> > > + struct drm_display_mode
> > > *adjusted_mode)
> > > +{
> > > + const struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
> >
> > Why const?
> > If no const, then ...
> >
> > > + unsigned long requested_link_freq =
> > > + mode->clock * fsl_ldb_link_freq_factor(fsl_ldb);
> >
> > ... this could be
> > unsigned long requested_link_freq =
> >
> > fsl_ldb_link_frequency(fsl_ldb,
> > mode->clock);
>
> I used fsl_ldb_link_freq_factor(fsl_ldb) to point out the symmetry to
> recalculate
> pclk = freq / fsl_ldb_link_freq_factor(fsl_ldb) below:
>
> > > + unsigned long freq = clk_round_rate(fsl_ldb->clk,
> > > requested_link_freq);
> > > +
> > > + if (freq != requested_link_freq) {
> > > + /*
> > > + * this will lead to flicker and incomplete lines
> > > on
> > > + * the attached display, adjust the CRTC clock
> > > + * accordingly.
> > > + */
> > > + int pclk = freq /
> > > fsl_ldb_link_freq_factor(fsl_ldb);
> >
> > I doubt that pixel clock tree cannot find appropriate division
> > ratios
> > for some pixel clock rates, especially for dual-link LVDS on
> > i.MX8MP
> > and i.MX93 platforms, because PLL clock rate should be 7x faster
> > than
> > pixel clock rate and 2x faster than "ldb" clock rate so that the
> > 3.5
> > folder between "ldb" clock and pixel clock can be met. That means
> > the
> > PLL clock rate needs to be explicitly set first for this case.
> >
> > Can you assign the PLL clock rate in DT to satisfy the "ldb" and
> > pixel
> > clock rates like the below commit does, if you use a LVDS panel?
> >
> > 4fbb73416b10 ("arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1
> > frequency to 506.8 MHz")
>
> I probably could. The point of my patch is you don't have to know in
> advance which LVDS panel is connected, and you don't have to
> calculate
> the base PLL clock by hand and store it in the device tree.
>
> In my test system, I have three different LVDS panels with EDID
> EEPROM,
> none of which worked with the stock driver, but all work with this
> patch.
> With slightly adapted pixel clocks though.
>
> The driver already warns if LDB and PCLK don't match, because this is
> a
> hardware constraint and violating this will lead to no image or image
> distortion. With the patch the driver tries to fix that.
>
> I don't know if it works for all or at least most panels, but for my
> panels
> it does. And if the clocks match, by chance or by refconfiguring the
> PLL
> base
> clock, the patch does nothing.
just as a data point, I'm very happy with this patch as it make my 51,2
MHz lvds panel just work without doing anything else. I'll happily
carry it along for v6.12 if it's not going into stable :)
martin
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