linux-kernel - RE: [PATCH 2/2] PCI: amd-mdb: Add AMD MDB Root Port driver

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Message-ID: <E73C5B2C-A594-49DB-9AF6-F2E3FDE972A4@linaro.org>
Date: Mon, 09 Dec 2024 15:24:45 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: "Havalige, Thippeswamy" <thippeswamy.havalige@....com>
CC: Bjorn Helgaas <helgaas@...nel.org>,
 "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
 "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
 "kw@...ux.com" <kw@...ux.com>, "robh@...nel.org" <robh@...nel.org>,
 "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
 "conor+dt@...nel.org" <conor+dt@...nel.org>,
 "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
 "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "jingoohan1@...il.com" <jingoohan1@...il.com>,
 "Simek, Michal" <michal.simek@....com>,
 "Gogada, Bharat Kumar" <bharat.kumar.gogada@....com>
Subject: RE: [PATCH 2/2] PCI: amd-mdb: Add AMD MDB Root Port driver



On December 9, 2024 3:14:15 PM GMT+05:30, "Havalige, Thippeswamy" <thippeswamy.havalige@....com> wrote:
>Hi Sadhasivam,
>
>> -----Original Message-----
>> From: manivannan.sadhasivam@...aro.org <manivannan.sadhasivam@...aro.org>
>> Sent: Sunday, December 8, 2024 6:29 PM
>> To: Havalige, Thippeswamy <thippeswamy.havalige@....com>
>> Cc: Bjorn Helgaas <helgaas@...nel.org>; bhelgaas@...gle.com;
>> lpieralisi@...nel.org; kw@...ux.com; robh@...nel.org; krzk+dt@...nel.org;
>> conor+dt@...nel.org; linux-pci@...r.kernel.org; devicetree@...r.kernel.org; linux-
>> kernel@...r.kernel.org; jingoohan1@...il.com; Simek, Michal
>> <michal.simek@....com>; Gogada, Bharat Kumar
>> <bharat.kumar.gogada@....com>
>> Subject: Re: [PATCH 2/2] PCI: amd-mdb: Add AMD MDB Root Port driver
>> 
>> On Mon, Dec 02, 2024 at 08:21:36AM +0000, Havalige, Thippeswamy wrote:
>> 
>> [...]
>> 
>> > > > +	d = irq_domain_get_irq_data(pcie->mdb_domain, irq);
>> > > > +	if (intr_cause[d->hwirq].str)
>> > > > +		dev_warn(dev, "%s\n", intr_cause[d->hwirq].str);
>> > > > +	else
>> > > > +		dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq);
>> > > > +
>> > > > +	return IRQ_HANDLED;
>> > >
>> > > I see that some of these messages are "Correctable/Non-Fatal/Fatal error
>> > > message"; I assume this Root Port doesn't have an AER Capability, and this
>> > > interrupt is the "System Error" controlled by the Root Control Error Enable bits in
>> the
>> > > PCIe Capability?  (See PCIe r6.0, sec 6.2.6)
>> > >
>> > > Is there any way to hook this into the AER handling so we can do something
>> about
>> > > it, since the devices *below* the Root Port may support AER and may have
>> useful
>> > > information logged?
>> > >
>> > > Since this is DWC-based, I suppose these are general questions that apply to all
>> > > the similar drivers.
>> >
>> >
>> > Thanks for review, We have this in our plan to hook platform specific error
>> interrupts
>> > to AER in future will add this support.
>> >
>> 
>> So on your platform, AER (also PME) interrupts are reported over SPI interrupt
>> only and not through MSI/MSI-X? Most of the DWC controllers have this weird
>> behavior of reporting AER/PME only through SPI, but that should be legacy
>> controllers. Newer ones does support MSI.
>
>Thanks for your comment, Yes our platform supports platform specific Error 
>Interrupts over SPI.
>

My question was specifically about whether your platform _only_ supports SPI or both SPI and MSI for AER/PME.

- Mani

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