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Message-ID: <87ed2flb6q.fsf@BLaptop.bootlin.com> Date: Tue, 10 Dec 2024 18:06:37 +0100 From: Gregory CLEMENT <gregory.clement@...tlin.com> To: kernel test robot <lkp@...el.com> Cc: oe-kbuild-all@...ts.linux.dev, linux-kernel@...r.kernel.org, Thomas Bogendoerfer <tsbogend@...ha.franken.de>, Théo Lebrun <theo.lebrun@...tlin.com> Subject: Re: arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: cast truncates bits from constant value (fffffffff000 becomes fffff000) Hello, > tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master > head: fac04efc5c793dccbd07e2d59af9f90b7fc0dca4 > commit: 6f14293257309a02a6d451e80e4ef1d78560479e MIPS: Allow using more than 32-bit addresses for reset vectors when possible > date: 6 weeks ago > config: mips-randconfig-r112-20241209 (https://download.01.org/0day-ci/archive/20241209/202412091227.KUZgstBB-lkp@intel.com/config) > compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 592c0fe55f6d9a811028b5f3507be91458ab2713) > reproduce: (https://download.01.org/0day-ci/archive/20241209/202412091227.KUZgstBB-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <lkp@...el.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202412091227.KUZgstBB-lkp@intel.com/ [...] > arch/mips/kernel/smp-cps.c: note: in included file (through arch/mips/include/asm/mips-cps.h): > arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@ > arch/mips/include/asm/mips-cm.h:329:1: sparse: expected void volatile [noderef] __iomem *mem > arch/mips/include/asm/mips-cm.h:329:1: sparse: got void * > arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@ > arch/mips/include/asm/mips-cm.h:329:1: sparse: expected void volatile [noderef] __iomem *mem > arch/mips/include/asm/mips-cm.h:329:1: sparse: got void * > arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@ > arch/mips/include/asm/mips-cm.h:329:1: sparse: expected void volatile [noderef] __iomem *mem > arch/mips/include/asm/mips-cm.h:329:1: sparse: got void * > arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got void * @@ > arch/mips/include/asm/mips-cm.h:329:1: sparse: expected void volatile [noderef] __iomem *mem > arch/mips/include/asm/mips-cm.h:329:1: sparse: got void * >>> arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: cast truncates bits from constant value (fffffffff000 becomes fffff000) > arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: incorrect type in return expression (different address spaces) @@ expected void * @@ got void [noderef] __iomem * @@ > arch/mips/include/asm/mips-cm.h:329:1: sparse: expected void * > arch/mips/include/asm/mips-cm.h:329:1: sparse: got void [noderef] __iomem * > arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: incorrect type in return expression (different address spaces) @@ expected void * @@ got void [noderef] __iomem * @@ > arch/mips/include/asm/mips-cm.h:329:1: sparse: expected void * > arch/mips/include/asm/mips-cm.h:329:1: sparse: got void [noderef] __iomem * > arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: incorrect type in return expression (different address spaces) @@ expected void * @@ got void [noderef] __iomem * @@ > arch/mips/include/asm/mips-cm.h:329:1: sparse: expected void * > arch/mips/include/asm/mips-cm.h:329:1: sparse: got void [noderef] __iomem * >>> arch/mips/include/asm/mips-cm.h:329:1: sparse: sparse: cast truncates bits from constant value (fffffffff000 becomes fffff000) So I looked for from where this error comes and found that it was caused by: write_gcr_co_reset64_base(CM_GCR_Cx_RESET64_BASE_BEVEXCBASE); in function check_64bit_reset() (smp-cps.c) The constant value being CM_GCR_Cx_RESET64_BASE_BEVEXCBASE. It occurs due to: __raw_writel(val, addr_##unit##_##name()); in write_##unit##_##name(uint##sz##_t val) (mips-cps.h) However, check_64bit_reset() is only called when mips_cm_is64 is true, whereas in write_##unit##_##name(uint##sz##_t val) __raw_writel is not called when mips_cm_is64 is true. This warning is therefore a false positive and I do not see any reasonable way to silence it, so I think we should simply ignore it unless someone has a better proposal. Gregory [...] > > vim +329 arch/mips/include/asm/mips-cm.h > > 326 > 327 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ > 328 GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) > > 329 GCR_CX_ACCESSOR_RW(64, 0x020, reset64_base) > 330 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) > 331 #define CM_GCR_Cx_RESET64_BASE_BEVEXCBASE GENMASK_ULL(47, 12) > 332 #define CM_GCR_Cx_RESET_BASE_MODE BIT(1) > 333 > > -- > 0-DAY CI Kernel Test Service > https://github.com/intel/lkp-tests/wiki -- Grégory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
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