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Message-ID: <87zfl3b18t.ffs@tglx>
Date: Tue, 10 Dec 2024 23:51:30 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Zhang Rui <rui.zhang@...el.com>, rafael@...nel.org, lenb@...nel.org,
mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com,
x86@...nel.org
Cc: rui.zhang@...el.com, linux-acpi@...r.kernel.org,
linux-kernel@...r.kernel.org, jmattson@...gle.com
Subject: Re: [PATCH] x86/acpi: Fix LAPIC/x2APIC parsing order
On Tue, Oct 22 2024 at 08:17, Zhang Rui wrote:
> On some systems, the same CPU (with the same APIC ID) is assigned a
> different logical CPU id after commit ec9aedb2aa1a ("x86/acpi: Ignore
> invalid x2APIC entries").
>
> This means that Linux enumerates the CPUs in a different order, which
> violates ACPI specification[1] that states:
>
> "OSPM should initialize processors in the order that they appear in
> the MADT"
>
> The problematic commit parses all LAPIC entries before any x2APIC
> entries, aiming to ignore x2APIC entries with APIC ID < 255 when valid
> LAPIC entries exist. However, it disrupts the CPU enumeration order on
> systems where x2APIC entries precede LAPIC entries in the MADT.
>
> Fix the problem by separately checking LAPIC entries before parsing any
> LAPIC or x2APIC entries.
I really had to stare at the change to understand how this fixes
anything. What you want to say is:
Fix this problem by:
1) Parsing LAPIC entries first without registering them in the
topology to evaluate whether valid LAPIC entries exist.
2) Restoring the MADT in order parser which invokes either the LAPIC or
the X2APIC parser function depending on the entry type.
The X2APIC parser still ignores entries < 0xff in case that #1
found valid LAPIC entries independent of their position in the
MADT table.
Other than that:
Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
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