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Message-ID:
<SN7PR12MB72014E558437E5B6E630E72E8B3D2@SN7PR12MB7201.namprd12.prod.outlook.com>
Date: Tue, 10 Dec 2024 06:37:52 +0000
From: "Havalige, Thippeswamy" <thippeswamy.havalige@....com>
To: Rob Herring <robh@...nel.org>
CC: "bhelgaas@...gle.com" <bhelgaas@...gle.com>, "lpieralisi@...nel.org"
<lpieralisi@...nel.org>, "kw@...ux.com" <kw@...ux.com>,
"manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>, "conor+dt@...nel.org"
<conor+dt@...nel.org>, "linux-pci@...r.kernel.org"
<linux-pci@...r.kernel.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "jingoohan1@...il.com"
<jingoohan1@...il.com>, "Simek, Michal" <michal.simek@....com>, "Gogada,
Bharat Kumar" <bharat.kumar.gogada@....com>
Subject: RE: [PATCH v2 1/2] dt-bindings: PCI: amd-mdb: Add AMD Versal2 MDB
PCIe Root Port Bridge
Hi Robh,
Thank you for your comments. I mistakenly mentioned Bjorn in my earlier message.
My apologies for the oversight.
Regards,
Thippeswamy H
> -----Original Message-----
> From: Havalige, Thippeswamy
> Sent: Wednesday, December 4, 2024 12:02 PM
> To: Rob Herring <robh@...nel.org>
> Cc: bhelgaas@...gle.com; lpieralisi@...nel.org; kw@...ux.com;
> manivannan.sadhasivam@...aro.org; krzk+dt@...nel.org; conor+dt@...nel.org;
> linux-pci@...r.kernel.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org; jingoohan1@...il.com; Simek, Michal
> <michal.simek@....com>; Gogada, Bharat Kumar
> <bharat.kumar.gogada@....com>
> Subject: RE: [PATCH v2 1/2] dt-bindings: PCI: amd-mdb: Add AMD Versal2 MDB
> PCIe Root Port Bridge
>
> Hi Bjorn,
>
> > -----Original Message-----
> > From: Rob Herring <robh@...nel.org>
> > Sent: Tuesday, December 3, 2024 8:11 PM
> > To: Havalige, Thippeswamy <thippeswamy.havalige@....com>
> > Cc: bhelgaas@...gle.com; lpieralisi@...nel.org; kw@...ux.com;
> > manivannan.sadhasivam@...aro.org; krzk+dt@...nel.org;
> > conor+dt@...nel.org; linux-pci@...r.kernel.org;
> > devicetree@...r.kernel.org; linux- kernel@...r.kernel.org;
> > jingoohan1@...il.com; Simek, Michal <michal.simek@....com>; Gogada,
> > Bharat Kumar <bharat.kumar.gogada@....com>
> > Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: amd-mdb: Add AMD Versal2
> > MDB PCIe Root Port Bridge
> >
> > On Tue, Dec 03, 2024 at 06:06:07PM +0530, Thippeswamy Havalige wrote:
> > > Add AMD Versal2 MDB (Multimedia DMA Bridge) PCIe Root Port Bridge.
> > >
> > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
> > > ---
> > > Changes in v2:
> > > -------------
> > > - Modify patch subject.
> > > - Add pcie host bridge reference.
> > > - Modify filename as per compatible string.
> > > - Remove standard PCI properties.
> > > - Modify interrupt controller description.
> > > - Indentation
> > > ---
> > > .../bindings/pci/amd,versal2-mdb-host.yaml | 132 ++++++++++++++++++
> > > 1 file changed, 132 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
> > > b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml
> > > new file mode 100644
> > > index 000000000000..75795bab8254
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yam
> > > +++ l
> > > @@ -0,0 +1,132 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/pci/amd,mdb-pcie.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller
> > > +
> > > +maintainers:
> > > + - Thippeswamy Havalige <thippeswamy.havalige@....com>
> > > +
> > > +allOf:
> > > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > > +
> > > +properties:
> > > + compatible:
> > > + const: amd,versal2-mdb-host
> > > +
> > > + reg:
> > > + items:
> > > + - description: MDB PCIe controller 0 SLCR
> >
> > SLCR is not defined anywhere.
> Thanks for review, Here SLCR refers to mdb_pcie_slcr should I modify it to lower
> case?
> >
> > > + - description: configuration region
> > > + - description: data bus interface
> > > + - description: address translation unit register
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: mdb_pcie_slcr
> > > + - const: config
> > > + - const: dbi
> > > + - const: atu
> >
> > DWC based it seems. You need to reference the DWC schema.
> - Thanks for the review, Here should I add both dwc and pci-host-bridge host bridge
> schema.
> > > +
> > > + ranges:
> > > + maxItems: 2
> > > +
> > > + msi-map:
> > > + maxItems: 1
> > > +
> > > + bus-range:
> > > + maxItems: 1
> >
> > Already defined in the common schema. Plus you obviously didn't test
> > anything with this because bus-range must be exactly 2 entries. 1 is not valid.
> - Thanks for the review, Will remove it in next patch.
> >
> > > +
> > > + "#address-cells":
> > > + const: 3
> > > +
> > > + "#size-cells":
> > > + const: 2
> >
> > Both of these are also already defined in the pci-host-bridge.yaml.
> Thanks for the review, Will update in next patch.
> >
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > +
> > > + interrupt-map-mask:
> > > + items:
> > > + - const: 0
> > > + - const: 0
> > > + - const: 0
> > > + - const: 7
> > > +
> > > + interrupt-map:
> > > + maxItems: 4
> > > +
> > > + "#interrupt-cells":
> > > + const: 1
> > > +
> > > + interrupt-controller:
> > > + description: identifies the node as an interrupt controller
> > > + type: object
> > > + properties:
> > > + interrupt-controller: true
> > > +
> > > + "#address-cells":
> > > + const: 0
> > > +
> > > + "#interrupt-cells":
> > > + const: 1
> > > +
> > > + required:
> > > + - interrupt-controller
> > > + - "#address-cells"
> > > + - "#interrupt-cells"
> > > +
> > > + additionalProperties: false
> >
> > Move this before 'properties'.
> - Thanks for the review, I will update in next patch.
> >
> > > +
> > > +required:
> > > + - reg
> > > + - reg-names
> > > + - interrupts
> > > + - interrupt-map
> > > + - interrupt-map-mask
> > > + - msi-map
> > > + - ranges
> >
> > Already required by common schema.
> Thanks for the review, will update in next patch.
> >
> > > + - "#interrupt-cells"
> > > + - interrupt-controller
> > > +
> > > +unevaluatedProperties: false
> > > +
> > > +examples:
> > > +
> >
> > Drop blank line.
> Thanks for the review, will update in next patch.
> >
> > > + - |
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > + soc {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + pci@...31000 {
> >
> > pcie@...
> Thanks for the review, will update in next patch.
> >
> > > + compatible = "amd,versal2-mdb-host";
> > > + reg = <0x0 0xed931000 0x0 0x2000>,
> > > + <0x1000 0x100000 0x0 0xff00000>,
> > > + <0x1000 0x0 0x0 0x100000>,
> > > + <0x0 0xed860000 0x0 0x2000>;
> > > + reg-names = "mdb_pcie_slcr", "config", "dbi", "atu";
> > > + ranges = <0x2000000 0x00 0xa8000000 0x00 0xa8000000
> > > + 0x00
> > 0x10000000>,
> > > + <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>;
> > > + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-parent = <&gic>;
> > > + interrupt-map-mask = <0 0 0 7>;
> > > + interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
> > > + <0 0 0 2 &pcie_intc_0 1>,
> > > + <0 0 0 3 &pcie_intc_0 2>,
> > > + <0 0 0 4 &pcie_intc_0 3>;
> > > + msi-map = <0x0 &gic_its 0x00 0x10000>;
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + #interrupt-cells = <1>;
> > > + device_type = "pci";
> > > + pcie_intc_0: interrupt-controller {
> > > + #address-cells = <0>;
> > > + #interrupt-cells = <1>;
> > > + interrupt-controller;
> > > + };
> > > + };
> > > + };
> > > --
> > > 2.34.1
> > >
> Regards,
> Thippeswamy H
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