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Message-ID: <62e4deb4-77ee-4937-8959-69de462f4d8e@linux.intel.com>
Date: Wed, 11 Dec 2024 15:13:21 -0500
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Namhyung Kim <namhyung@...nel.org>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>,
James Clark <james.clark@...aro.org>, Ravi Bangoria <ravi.bangoria@....com>,
Atish Patra <atishp@...shpatra.org>, Mingwei Zhang <mizhang@...gle.com>,
Kajol Jain <kjain@...ux.ibm.com>, Thomas Richter <tmricht@...ux.ibm.com>,
Palmer Dabbelt <palmer@...osinc.com>, Adrian Hunter
<adrian.hunter@...el.com>, Ian Rogers <irogers@...gle.com>,
Jiri Olsa <jolsa@...nel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-perf-users@...r.kernel.org
Subject: Re: [REGRESSION] 'perf mem record' on a Intel hybrid system broken
On 2024-12-11 1:48 p.m., Namhyung Kim wrote:
> On Wed, Dec 11, 2024 at 12:55:03PM -0500, Liang, Kan wrote:
>> On 2024-12-04 2:24 p.m., Namhyung Kim wrote:
>>> I think I got a related report from the kernel test robot but it was a
>>> Sapphire Rapids machine. I don't have a Intel hybrid machine in hand.
>>> I'll try to take a look at it on Sapphire Rapids.
>>
>> The default precise_ip level for perf mem is always 3.
>>
>> For the latest intel platforms, it implies PDist, which is only
>> available on GP 0.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/events/intel/core.c#n4412
>>
>> However, the mem-load PEBS event is available on all GP counters but GP
>> 0. :(
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/events/intel/ds.c#n1176
>>
>> So the precise_ip-- is required.
>>
>> The failure of scheduling returns -EINVAL.
>>
>> But Namhyung's patch assumes that the kernel return -EOPNOTSUPP when PMU
>> doesn't support the given precise level.
>> (Sorry, I didn't notice the case early.)
>>
>> Is it possible to reduce the precise_ip for the -EINVAL as well?
>
> Sure, please see https://lore.kernel.org/r/Z1DV0lN8qHSysX7f@google.com
>
Thanks for the fix. It looks good to me.
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
Thanks,
Kan
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