linux-kernel - Re: [PATCH v6 2/5] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC

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Message-ID: <a3ddacc9-73cd-4214-9a39-5aaaa91fc93e@quicinc.com>
Date: Fri, 13 Dec 2024 18:19:40 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson
	<andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen
 Boyd" <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Catalin Marinas
	<catalin.marinas@....com>,
        Will Deacon <will@...nel.org>, Konrad Dybcio
	<konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <quic_kkumarcs@...cinc.com>,
        <quic_suruchia@...cinc.com>, <quic_pavir@...cinc.com>,
        <quic_linchen@...cinc.com>, <quic_leiwei@...cinc.com>,
        <bartosz.golaszewski@...aro.org>, <srinivas.kandagatla@...aro.org>
Subject: Re: [PATCH v6 2/5] clk: qcom: Add CMN PLL clock controller driver for
 IPQ SoC



On 12/13/2024 2:30 AM, Konrad Dybcio wrote:
> On 7.11.2024 10:50 AM, Luo Jie wrote:
>> The CMN PLL clock controller supplies clocks to the hardware
>> blocks that together make up the Ethernet function on Qualcomm
>> IPQ SoCs and to GCC. The driver is initially supported for
>> IPQ9574 SoC.
>>
>> The CMN PLL clock controller expects a reference input clock
>> from the on-board Wi-Fi block acting as clock source. The input
>> reference clock needs to be configured to one of the supported
>> clock rates.
>>
>> The controller supplies a number of fixed-rate output clocks.
>> For the IPQ9574, there is one output clock of 353 MHZ to PPE
>> (Packet Process Engine) hardware block, three 50 MHZ output
>> clocks and an additional 25 MHZ output clock supplied to the
>> connected Ethernet devices. The PLL also supplies a 24 MHZ
>> clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25
>> MHZ clock to PCS.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
> 
> [...]
> 
>> +	/* Enable PLL locked detect. */
>> +	ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_CTRL,
>> +				 CMN_PLL_CTRL_LOCK_DETECT_EN,
>> +				 CMN_PLL_CTRL_LOCK_DETECT_EN);
>> +	if (ret)
> 
> you can streamline these with regmap_set/clear_bits

Ok, thanks, I will update to use it.

> 
>> +		return ret;
>> +
>> +	/*
>> +	 * Reset the CMN PLL block to ensure the updated configurations
>> +	 * take effect.
>> +	 */
>> +	ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
>> +				 CMN_ANA_EN_SW_RSTN, 0);
>> +	if (ret)
>> +		return ret;
>> +
>> +	usleep_range(1000, 1200);
>> +	ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
>> +				 CMN_ANA_EN_SW_RSTN, CMN_ANA_EN_SW_RSTN);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Stability check of CMN PLL output clocks. */
>> +	return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val,
>> +					(val & CMN_PLL_CLKS_LOCKED),
>> +					100, 100 * USEC_PER_MSEC);
>> +}
> 
> [...]
> 
>> +static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	int ret;
>> +
>> +	ret = devm_pm_runtime_enable(dev);
>> +	if (ret)
>> +		return ret;
>> +
>> +	ret = devm_pm_clk_create(dev);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/*
>> +	 * To access the CMN PLL registers, the GCC AHB & SYSY clocks
> 
> SYS?
> 
> Konrad

Yes, I will correct it.