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Message-Id: <20241213114233.12388-2-luxu.kernel@bytedance.com>
Date: Fri, 13 Dec 2024 19:42:32 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: tjeznach@...osinc.com,
joro@...tes.org,
will@...nel.org
Cc: lihangjing@...edance.com,
xieyongji@...edance.com,
guojinhui.liam@...edance.com,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Xu Lu <luxu.kernel@...edance.com>
Subject: [PATCH 1/2] iommu/riscv: Empty iommu queue before enabling it
Changing cqen/fqen/pqen from 0 to 1 sets the cqh/fqt/pqt registers to 0.
But the cqt/fqh/pqh registers are left unmodified. This commit resets
cqt/fqh/pqh registers to ensure corresponding queues are empty before
being enabled during initialization.
Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
---
drivers/iommu/riscv/iommu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 8a05def774bd..84806724f568 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -240,6 +240,12 @@ static int riscv_iommu_queue_enable(struct riscv_iommu_device *iommu,
return rc;
}
+ /* Empty queue before enabling it */
+ if (queue->qid == RISCV_IOMMU_INTR_CQ)
+ riscv_iommu_writel(queue->iommu, Q_TAIL(queue), 0);
+ else
+ riscv_iommu_writel(queue->iommu, Q_HEAD(queue), 0);
+
/*
* Enable queue with interrupts, clear any memory fault if any.
* Wait for the hardware to acknowledge request and activate queue
--
2.20.1
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