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Message-ID:
<OSBPR01MB277516153173A68AEDAE0FCFFF392@OSBPR01MB2775.jpnprd01.prod.outlook.com>
Date: Sat, 14 Dec 2024 04:36:15 +0000
From: John Madieu <john.madieu.xa@...renesas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
CC: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, Biju
Das <biju.das.jz@...renesas.com>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Claudiu Beznea
<claudiu.beznea.uj@...renesas.com>, "john.madieu@...il.com"
<john.madieu@...il.com>, "linux-renesas-soc@...r.kernel.org"
<linux-renesas-soc@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>
Subject: RE: [PATCH 3/5] soc: renesas: rz-sysc: Add support for RZ/G3E family
> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: Friday, December 13, 2024 5:25 PM
> Subject: Re: [PATCH 3/5] soc: renesas: rz-sysc: Add support for RZ/G3E
> family
>
> Hi John,
Hello Geert,
>
> On Fri, Dec 6, 2024 at 10:26 PM John Madieu
> <john.madieu.xa@...renesas.com> wrote:
> > Add SoC detection support for RZ/G3E SoC. Also add support for
> > detecting the number of cores and ETHOS-U55 NPU and also detect PLL
> > mismatch for SW settings other than 1.7GHz.
> >
> > Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/soc/renesas/Kconfig
> > +++ b/drivers/soc/renesas/Kconfig
> > @@ -348,6 +348,7 @@ config ARCH_R9A09G011
> >
> > config ARCH_R9A09G047
> > bool "ARM64 Platform support for RZ/G3E"
> > + select SYSC_R9A09G047
> > help
> > This enables support for the Renesas RZ/G3E SoC variants.
> >
> > @@ -386,9 +387,14 @@ config RST_RCAR
> >
> > config SYSC_RZ
> > bool "System controller for RZ SoCs" if COMPILE_TEST
> > + depends on MFD_SYSCON
>
> WARNING: unmet direct dependencies detected for SYSC_RZ
> Depends on [n]: SOC_RENESAS [=y] && MFD_SYSCON [=n]
> Selected by [y]:
> - SYSC_R9A08G045 [=y] && SOC_RENESAS [=y]
> - SYSC_R9A09G047 [=y] && SOC_RENESAS [=y]
>
> So please select MFD_SYSCON instead.
Will be done in v2.
>
> >
> > config SYSC_R9A08G045
> > bool "Renesas RZ/G3S System controller support" if COMPILE_TEST
> > select SYSC_RZ
> >
> > +config SYSC_R9A09G047
> > + bool "Renesas RZ/G3E System controller support" if COMPILE_TEST
> > + select SYSC_RZ
> > +
> > endif # SOC_RENESAS
>
> > --- /dev/null
> > +++ b/drivers/soc/renesas/r9a09g047-sysc.c
> > @@ -0,0 +1,70 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * RZ/G3E System controller driver
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/device.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +
> > +#include "rz-sysc.h"
> > +
> > +/* Register definitions */
> > +#define SYS_LSI_DEVID 0x304
> > +#define SYS_LSI_MODE 0x300
> > +#define SYS_LSI_PRR 0x308
> > +#define SYS_LSI_DEVID_REV GENMASK(31, 28)
> > +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0)
> > +#define SYS_LSI_PRR_CA55_DIS BIT(8)
> > +#define SYS_LSI_PRR_NPU_DIS BIT(1)
> > +/*
> > + * BOOTPLLCA[1:0]
> > + * [0,0] => 1.1GHZ
> > + * [0,1] => 1.5GHZ
> > + * [1,0] => 1.6GHZ
> > + * [1,1] => 1.7GHZ
> > + */
> > +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
> > +#define SYS_LSI_MODE_CA55_1_7GHz 0x3
>
> Please align the second column, and please group register offsets and bits
> together.
Noted.
>
> > +
> > +static void rzg3e_extended_device_identification(struct device *dev,
> > + void __iomem *sysc_base,
> > + struct soc_device_attribute
> > +*soc_dev_attr) {
> > + u32 prr_val, mode_val;
> > + bool is_quad_core, npu_enabled;
> > +
> > + prr_val = readl(sysc_base + SYS_LSI_PRR);
> > + mode_val = readl(sysc_base + SYS_LSI_MODE);
> > +
> > + /* Check CPU and NPU configuration */
> > + is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
> > + npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
> > +
> > + dev_info(dev, "Detected Renesas %s Core %s %s Rev %s %s\n",
>
> There are two spaces before the last %s.
> Please drop both spaces...
>
> > + is_quad_core ? "Quad" : "Dual",
> > + soc_dev_attr->family,
> > + soc_dev_attr->soc_id,
> > + soc_dev_attr->revision,
> > + npu_enabled ? "with Ethos-U55" : "");
>
> ... and add one space here, just before "with".
Thanks for the hint.
>
> > +
> > + /* Check CA55 PLL configuration */
> > + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) !=
> SYS_LSI_MODE_CA55_1_7GHz)
> > + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
>
> Just wondering: is that a problem? Can't it be handled in the clock
> driver?
The current implementation supports only 1.7GHz, /2, /4, /8 frequencies,
hence, the warning.
>
> > +}
>
> > --- a/drivers/soc/renesas/rz-sysc.c
> > +++ b/drivers/soc/renesas/rz-sysc.c
> > @@ -231,7 +231,7 @@ static int rz_sysc_soc_init(struct rz_sysc *sysc,
> > const struct of_device_id *mat
> >
> > soc_id_start = strchr(match->compatible, ',') + 1;
> > soc_id_end = strchr(match->compatible, '-');
> > - size = soc_id_end - soc_id_start;
> > + size = soc_id_end - soc_id_start + 1;
>
> Unrelated fix?
I guess so. Was thinking of moving it in a separate patch in the v2
as suggested by Claudiu.
>
> > if (size > 32)
> > size = 32;
> > strscpy(soc_id, soc_id_start, size);
>
> > @@ -315,20 +326,25 @@ static int rz_sysc_probe(struct platform_device
> *pdev)
> > return ret;
> >
> > data = match->data;
> > - if (!data->max_register_offset)
> > - return -EINVAL;
> > + if (data->signals_init_data) {
>
> if (!data->signals_init_data)
> return 0;
Thanks for the hint.
>
> > + if (!data->max_register_offset)
> > + return -EINVAL;
> >
> > - ret = rz_sysc_signals_init(sysc, data->signals_init_data, data-
> >num_signals);
> > - if (ret)
> > - return ret;
> > + ret = rz_sysc_signals_init(sysc, data-
> >signals_init_data, data->num_signals);
> > + if (ret)
> > + return ret;
> > +
> > + rz_sysc_regmap.max_register = data->max_register_offset;
> > + dev_set_drvdata(dev, sysc);
> >
> > - dev_set_drvdata(dev, sysc);
> > - rz_sysc_regmap.max_register = data->max_register_offset;
> > - regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap);
> > - if (IS_ERR(regmap))
> > - return PTR_ERR(regmap);
> > + regmap = devm_regmap_init(dev, NULL, sysc,
> &rz_sysc_regmap);
> > + if (IS_ERR(regmap))
> > + return PTR_ERR(regmap);
> >
> > - return of_syscon_register_regmap(dev->of_node, regmap);
> > + return of_syscon_register_regmap(dev->of_node, regmap);
> > + }
> > +
> > + return 0;
> > }
> >
> > static struct platform_driver rz_sysc_driver = {
>
> > --- a/drivers/soc/renesas/rz-sysc.h
> > +++ b/drivers/soc/renesas/rz-sysc.h
> > @@ -42,6 +44,7 @@ struct rz_sysc_signal {
> > * @offset: SYSC SoC ID register offset
> > * @revision_mask: SYSC SoC ID revision mask
> > * @specific_id_mask: SYSC SoC ID specific ID mask
> > + * @extended_device_identification: SoC-specific extended device
> > + identification
> > */
> > struct rz_sysc_soc_id_init_data {
> > const char * const family;
> > @@ -49,6 +52,9 @@ struct rz_sysc_soc_id_init_data {
> > u32 offset;
> > u32 revision_mask;
> > u32 specific_id_mask;
> > + void (*extended_device_identification)(struct device *dev,
> > + void __iomem *sysc_base,
> > + struct soc_device_attribute *soc_dev_attr);
>
> That's a rather long name...
Will be shortened in v2. I'm thinking of ext_dev_id().
>
> > };
> >
> > /**
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
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