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Message-ID: <20241216075819.2066772-5-larisa.grigore@oss.nxp.com>
Date: Mon, 16 Dec 2024 09:58:14 +0200
From: Larisa Grigore <larisa.grigore@....nxp.com>
To: Frank.Li@....com
Cc: dmaengine@...r.kernel.org,
imx@...ts.linux.dev,
linux-kernel@...r.kernel.org,
s32@....com,
Christophe Lizzi <clizzi@...hat.com>,
Alberto Ruiz <aruizrui@...hat.com>,
Enric Balletbo <eballetb@...hat.com>,
Larisa Grigore <larisa.grigore@....nxp.com>
Subject: [PATCH 4/8] dmaengine: fsl-edma: add eDMAv3 registers to edma_regs
Add edma3_regs to match eDMAv3 new register layout for manage page (MP).
Introduce helper function fsl_edma3_setup_regs() to initialize the
edma_regs for eDMAv3, which pave the road to support S32 chips.
Signed-off-by: Larisa Grigore <larisa.grigore@....nxp.com>
---
drivers/dma/fsl-edma-common.c | 15 +++++++++++++++
drivers/dma/fsl-edma-common.h | 11 ++++++++++-
drivers/dma/fsl-edma-main.c | 8 +++++---
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index b132a88dfdec..62d51b269e54 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -44,6 +44,11 @@
#define EDMA64_ERRH 0x28
#define EDMA64_ERRL 0x2c
+#define EDMA_V3_MP_CSR 0x00
+#define EDMA_V3_MP_ES 0x04
+#define EDMA_V3_MP_INT 0x08
+#define EDMA_V3_MP_HRS 0x0C
+
void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
{
spin_lock(&fsl_chan->vchan.lock);
@@ -904,4 +909,14 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
}
}
+void fsl_edma3_setup_regs(struct fsl_edma_engine *edma)
+{
+ struct edma_regs *regs = &edma->regs;
+
+ regs->cr = edma->membase + EDMA_V3_MP_CSR;
+ regs->es = edma->membase + EDMA_V3_MP_ES;
+ regs->v3.is = edma->membase + EDMA_V3_MP_INT;
+ regs->v3.hrs = edma->membase + EDMA_V3_MP_HRS;
+}
+
MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index f1362daaa347..52901623d6fc 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -139,10 +139,18 @@ struct edma2_regs {
void __iomem *errl;
};
+struct edma3_regs {
+ void __iomem *is;
+ void __iomem *hrs;
+};
+
struct edma_regs {
void __iomem *cr;
void __iomem *es;
- struct edma2_regs v2;
+ union {
+ struct edma2_regs v2;
+ struct edma3_regs v3;
+ };
};
struct fsl_edma_sw_tcd {
@@ -491,5 +499,6 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
void fsl_edma_free_chan_resources(struct dma_chan *chan);
void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
+void fsl_edma3_setup_regs(struct fsl_edma_engine *edma);
#endif /* _FSL_EDMA_COMMON_H_ */
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 0b89c31bf38c..cc1787698b56 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -495,10 +495,12 @@ static int fsl_edma_probe(struct platform_device *pdev)
if (IS_ERR(fsl_edma->membase))
return PTR_ERR(fsl_edma->membase);
- if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
+ if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
fsl_edma_setup_regs(fsl_edma);
- regs = &fsl_edma->regs;
- }
+ else
+ fsl_edma3_setup_regs(fsl_edma);
+
+ regs = &fsl_edma->regs;
if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
--
2.47.0
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