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Message-ID: <20241216-ipq_pcs_6-13_rc1-v3-1-3abefda0fc48@quicinc.com>
Date: Mon, 16 Dec 2024 21:40:23 +0800
From: Lei Wei <quic_leiwei@...cinc.com>
To: Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller"
<davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
<kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit
<hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>
CC: <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<quic_kkumarcs@...cinc.com>, <quic_suruchia@...cinc.com>,
<quic_pavir@...cinc.com>, <quic_linchen@...cinc.com>,
<quic_luoj@...cinc.com>, <quic_leiwei@...cinc.com>,
<srinivas.kandagatla@...aro.org>, <bartosz.golaszewski@...aro.org>,
<vsmuthu@....qualcomm.com>, <john@...ozen.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org>
Subject: [PATCH net-next v3 1/5] dt-bindings: net: pcs: Add Ethernet PCS
for Qualcomm IPQ9574 SoC
The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes
functions. It supports different interface modes to enable Ethernet
MAC connections to different types of external PHYs/switch. It includes
PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions
for 10Gbps interface modes. There are three UNIPHY (PCS) instances
in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet
ports.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Signed-off-by: Lei Wei <quic_leiwei@...cinc.com>
---
.../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 190 +++++++++++++++++++++
include/dt-bindings/net/qcom,ipq9574-pcs.h | 15 ++
2 files changed, 205 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
new file mode 100644
index 000000000000..74573c28d6fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
@@ -0,0 +1,190 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ethernet PCS for Qualcomm IPQ9574 SoC
+
+maintainers:
+ - Lei Wei <quic_leiwei@...cinc.com>
+
+description:
+ The UNIPHY hardware blocks in the Qualcomm IPQ SoC include PCS and SerDes
+ functions. They enable connectivity between the Ethernet MAC inside the
+ PPE (packet processing engine) and external Ethernet PHY/switch. There are
+ three UNIPHY instances in IPQ9574 SoC which provide PCS functions to the
+ six Ethernet ports.
+
+ For SGMII (1Gbps PHY) or 2500BASE-X (2.5Gbps PHY) interface modes, the PCS
+ function is enabled by using the PCS block inside UNIPHY. For USXGMII (10Gbps
+ PHY), the XPCS block in UNIPHY is used.
+
+ The SerDes provides 125M (1Gbps mode) or 312.5M (2.5Gbps and 10Gbps modes)
+ RX and TX clocks to the NSSCC (Networking Sub System Clock Controller). The
+ NSSCC divides these clocks and generates the MII RX and TX clocks to each
+ of the MII interfaces between the PCS and MAC, as per the link speeds and
+ interface modes.
+
+ Different IPQ SoC may support different number of UNIPHYs (PCSes) since the
+ number of ports and their capabilities can be different between these SoCs
+
+ Below diagram depicts the UNIPHY (PCS) connections for an IPQ9574 SoC based
+ board. In this example, the PCS0 has four GMIIs/XGMIIs, which can connect
+ with four MACs to support QSGMII (4 x 1Gbps) or 10G_QXGMII (4 x 2.5Gbps)
+ interface modes.
+
+ - +-------+ +---------+ +-------------------------+
+ +---------+CMN PLL| | GCC | | NSSCC (Divider) |
+ | +----+--+ +----+----+ +--+-------+--------------+
+ | | | ^ |
+ | 31.25M | SYS/AHB|clk RX/TX|clk +------------+
+ | ref clk| | | | |
+ | | v | MII RX|TX clk MAC| RX/TX clk
+ |25/50M +--+---------+----------+-------+---+ +-+---------+
+ |ref clk | | +----------------+ | | | | PPE |
+ v | | | UNIPHY0 V | | V |
+ +-------+ | v | +-----------+ (X)GMII| | |
+ | | | +---+---+ | |--------|------|-- MAC0 |
+ | | | | | | | (X)GMII| | |
+ | Quad | | |SerDes | | PCS/XPCS |--------|------|-- MAC1 |
+ | +<----+ | | | | (X)GMII| | |
+ |(X)GPHY| | | | | |--------|------|-- MAC2 |
+ | | | | | | | (X)GMII| | |
+ | | | +-------+ | |--------|------|-- MAC3 |
+ +-------+ | | | | | |
+ | +-----------+ | | |
+ +-----------------------------------+ | |
+ +--+---------+----------+-------+---+ | |
+ +-------+ | UNIPHY1 | | |
+ | | | +-----------+ | | |
+ |(X)GPHY| | +-------+ | | (X)GMII| | |
+ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC4 |
+ | | | | | | | | | |
+ +-------+ | +-------+ | | | | |
+ | +-----------+ | | |
+ +-----------------------------------+ | |
+ +--+---------+----------+-------+---+ | |
+ +-------+ | UNIPHY2 | | |
+ | | | +-----------+ | | |
+ |(X)GPHY| | +-------+ | | (X)GMII| | |
+ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC5 |
+ | | | | | | | | | |
+ +-------+ | +-------+ | | | | |
+ | +-----------+ | | |
+ +-----------------------------------+ +-----------+
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq9574-pcs
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ clocks:
+ items:
+ - description: System clock
+ - description: AHB clock needed for register interface access
+
+ clock-names:
+ items:
+ - const: sys
+ - const: ahb
+
+ '#clock-cells':
+ const: 1
+ description: See include/dt-bindings/net/qcom,ipq9574-pcs.h for constants
+
+patternProperties:
+ '^pcs-mii@[0-4]$':
+ type: object
+ description: PCS MII interface.
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 4
+ description: MII index
+
+ clocks:
+ items:
+ - description: PCS MII RX clock
+ - description: PCS MII TX clock
+
+ clock-names:
+ items:
+ - const: rx
+ - const: tx
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+
+ ethernet-pcs@...0000 {
+ compatible = "qcom,ipq9574-pcs";
+ reg = <0x7a00000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_AHB_CLK>;
+ clock-names = "sys",
+ "ahb";
+ #clock-cells = <1>;
+
+ pcs-mii@0 {
+ reg = <0>;
+ clocks = <&nsscc 116>,
+ <&nsscc 117>;
+ clock-names = "rx",
+ "tx";
+ };
+
+ pcs-mii@1 {
+ reg = <1>;
+ clocks = <&nsscc 118>,
+ <&nsscc 119>;
+ clock-names = "rx",
+ "tx";
+ };
+
+ pcs-mii@2 {
+ reg = <2>;
+ clocks = <&nsscc 120>,
+ <&nsscc 121>;
+ clock-names = "rx",
+ "tx";
+ };
+
+ pcs-mii@3 {
+ reg = <3>;
+ clocks = <&nsscc 122>,
+ <&nsscc 123>;
+ clock-names = "rx",
+ "tx";
+ };
+ };
diff --git a/include/dt-bindings/net/qcom,ipq9574-pcs.h b/include/dt-bindings/net/qcom,ipq9574-pcs.h
new file mode 100644
index 000000000000..96bd036aaa70
--- /dev/null
+++ b/include/dt-bindings/net/qcom,ipq9574-pcs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Device Tree constants for the Qualcomm IPQ9574 PCS
+ */
+
+#ifndef _DT_BINDINGS_PCS_QCOM_IPQ9574_H
+#define _DT_BINDINGS_PCS_QCOM_IPQ9574_H
+
+/* The RX and TX clocks which are provided from the SerDes to NSSCC. */
+#define PCS_RX_CLK 0
+#define PCS_TX_CLK 1
+
+#endif /* _DT_BINDINGS_PCS_QCOM_IPQ9574_H */
--
2.34.1
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