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Message-ID: <20241217214929.GA1121691@yaz-khff2.amd.com>
Date: Tue, 17 Dec 2024 16:49:29 -0500
From: Yazen Ghannam <yazen.ghannam@....com>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
	Lukas Wunner <lukas@...ner.de>, Borislav Petkov <bp@...en8.de>,
	linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org,
	Mahesh J Salgaonkar <mahesh@...ux.ibm.com>,
	Oliver O'Halloran <oohall@...il.com>,
	Tony Luck <tony.luck@...el.com>
Subject: Re: [PATCH 0/3] PCI: Add support for logging Flit Mode TLPs (PCIe6)

On Fri, Jun 14, 2024 at 06:09:18PM +0300, Ilpo Järvinen wrote:
> This series adds support for Flit Mode (PCIe6). The series is built on
> top of the TLP Logging refactoring series:
> 
>   https://lore.kernel.org/linux-pci/20240514113109.6690-1-ilpo.jarvinen@linux.intel.com/
> 
> Important note to maintainer: The series carries
> pcie_update_link_speed() refactoring change that is almost identical
> with a patch in the PCIe BW controller series. The patch itself is
> basically the same but the context has minor difference. This will need
> to be considered if applying both series within the same kernel cycle.
> 
> Ilpo Järvinen (3):
>   PCI: Refactor pcie_update_link_speed()
>   PCI: Track Flit Mode Status & print it with link status
>   PCI: Handle TLP Log in Flit mode
> 
>  drivers/pci/hotplug/pciehp_hpc.c |  5 +--
>  drivers/pci/pci.c                | 12 ++++---
>  drivers/pci/pci.h                | 13 ++++++--
>  drivers/pci/pcie/aer.c           |  4 ++-
>  drivers/pci/pcie/dpc.c           | 23 ++++++++++---
>  drivers/pci/pcie/tlp.c           | 57 ++++++++++++++++++++++----------
>  drivers/pci/probe.c              | 13 +++++---
>  include/linux/aer.h              | 13 ++++++--
>  include/linux/pci.h              |  1 +
>  include/ras/ras_event.h          | 12 +++----
>  include/uapi/linux/pci_regs.h    |  6 +++-
>  11 files changed, 112 insertions(+), 47 deletions(-)
> 
> -- 
> 

Hi Ilpo, et al.,

Is there any new development on this feature? Or is it on hold while any
spec oversights are worked out in the PCI-SIG?

Thanks,
Yazen

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