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Message-ID: <20241217073854.3346051-1-chenhuacai@loongson.cn>
Date: Tue, 17 Dec 2024 15:38:54 +0800
From: Huacai Chen <chenhuacai@...ngson.cn>
To: Huacai Chen <chenhuacai@...nel.org>
Cc: loongarch@...ts.linux.dev,
Xuefeng Li <lixuefeng@...ngson.cn>,
Guo Ren <guoren@...nel.org>,
Xuerui Wang <kernel@...0n.name>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
linux-kernel@...r.kernel.org,
loongson-kernel@...ts.loongnix.cn,
Huacai Chen <chenhuacai@...ngson.cn>,
Chao Li <lichao@...ngson.cn>,
Juxin Gao <gaojuxin@...ngson.cn>
Subject: [PATCH] LoongArch: Correct the cacheinfo sharing information
SMT cores and their sibling cores share the same L1 and L2 private
caches (of course last level cache is also shared), so correct the
cacheinfo sharing information to let shared_cpu_map correctly reflect
this relationship.
Below is the output of "lscpu" on Loongson-3A6000 (4 cores, 8 threads).
1. Before patch:
L1d: 512 KiB (8 instances)
L1i: 512 KiB (8 instances)
L2: 2 MiB (8 instances)
L3: 16 MiB (1 instance)
2. After patch:
L1d: 256 KiB (4 instances)
L1i: 256 KiB (4 instances)
L2: 1 MiB (4 instances)
L3: 16 MiB (1 instance)
Reported-by: Chao Li <lichao@...ngson.cn>
Signed-off-by: Juxin Gao <gaojuxin@...ngson.cn>
Signed-off-by: Huacai Chen <chenhuacai@...ngson.cn>
---
arch/loongarch/kernel/cacheinfo.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/loongarch/kernel/cacheinfo.c b/arch/loongarch/kernel/cacheinfo.c
index c7988f757281..0d28228d0a8a 100644
--- a/arch/loongarch/kernel/cacheinfo.c
+++ b/arch/loongarch/kernel/cacheinfo.c
@@ -51,6 +51,12 @@ static void cache_cpumap_setup(unsigned int cpu)
continue;
sib_leaf = sib_cpu_ci->info_list + index;
+ /* SMT cores share all caches */
+ if (cpus_are_siblings(i, cpu)) {
+ cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
+ cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
+ }
+ /* Node's cores share shared caches */
if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
--
2.43.5
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